[llvm-bugs] [Bug 39490] New: Make -verbose-asm or another MC tool produce liveness and other pretty info in the asm dump
via llvm-bugs
llvm-bugs at lists.llvm.org
Mon Oct 29 15:25:28 PDT 2018
https://bugs.llvm.org/show_bug.cgi?id=39490
Bug ID: 39490
Summary: Make -verbose-asm or another MC tool produce liveness
and other pretty info in the asm dump
Product: libraries
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: Common Code Generator Code
Assignee: unassignedbugs at nondot.org
Reporter: clattner at nondot.org
CC: llvm-bugs at lists.llvm.org
Just a random idea based on this web page, but it would be interesting to build
an MC tool or enhance -verbose asm to include info like this tool:
https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html#cuobjdump
"nvdisasm is capable of showing the register (CC, general and predicate)
liveness range information. For each line of CUDA assembly, nvdisasm displays
whether a given device register was assigned, accessed, live or re-assigned. It
also shows the total number of registers used. This is useful if the user is
interested in the life range of any particular register, or register usage in
general."
The dump looks like this - I'm not sure if bugzilla will mangle this, if so,
look at the web page just below that paragraph:
//
+------+---------------+-----+
// | CC | GPR
|PRED |
// | |
0000000000 | |
// | # 01 | #
0123456789 | # 0 |
//
+------+---------------+-----+
_main10acosParams // | |
| |
_main10acosParams, at function // | |
| |
_main10acosParams,(.L_17 - _Z9acos_main10acosParams) // | |
| |
_main10acosParams,@"STO_CUDA_ENTRY STV_DEFAULT" // | |
| |
// | |
| |
// | |
| |
MOV R1, c[0x0][0x44]; // | | 1 ^
| |
S2R R0, SR_CTAID.X; // | | 2 ^:
| |
S2R R3, SR_TID.X; // | | 3 :: ^
| |
IMAD R3, R0, c[0x0][0x28], R3; // | | 3 v: x
| |
MOV R0, c[0x0][0x28]; // | | 3 ^: :
| |
ISETP.GE.AND P0, PT, R3, c[0x0][0x150], PT; // | | 3 :: v
| 1 ^ |
IMUL R0, R0, c[0x0][0x34]; // | | 3 x: :
| 1 : |
@P0 EXIT; // | | 3 :: :
| 1 v |
MOV32I R8, 0x4; // | | 4 :: :
^ | |
MOV32I R9, 0x3c94d2e9; // | | 5 :: :
:^ | |
NOP; // | | 5 :: :
:: | |
NOP; // | | 5 :: :
:: | |
NOP; // | | 5 :: :
:: | |
NOP; // | | 5 :: :
:: | |
// | | 5 :: :
:: | |
IMAD R6.CC, R3, R8, c[0x0][0x140]; // | 1 ^ | 6 :: v
^ v: | |
IMAD.HI.X R7, R3, R8, c[0x0][0x144]; // | 1 v | 7 :: v
:^v: | |
LD.E R2, [R6]; // | | 8 ::^:
vv:: | |
FADD.FTZ R4, -|R2|, 1; // | | 7 ::v:^
:: | |
FSETP.GT.FTZ.AND P0, PT, |R2|, c[0x2][0x0], PT; // | | 7 ::v::
:: | 1 ^ |
FMUL.FTZ R4, R4, 0.5; // | | 7 ::::x
:: | 1 : |
F2F.FTZ.F32.F32 R5, |R2|; // | | 8 ::v::^
:: | 1 : |
MUFU.RSQ R4, R4; // | | 8 ::::x:
:: | 1 : |
@P0 MUFU.RCP R5, R4; // | | 8 ::::v^
:: | 1 v |
FMUL.FTZ R4, R5, R5; // | | 8 ::::^v
:: | 1 : |
IMAD R6.CC, R3, R8, c[0x0][0x148]; // | 1 ^ | 9
:::v::^ v: | 1 : |
FFMA.FTZ R7, R4, c[0x2][0x4], R9; // | 1 : | 10
::::v::^:v | 1 : |
FFMA.FTZ R7, R7, R4, c[0x2][0x8]; // | 1 : | 10
::::v::x:: | 1 : |
FFMA.FTZ R7, R7, R4, c[0x2][0xc]; // | 1 : | 10
::::v::x:: | 1 : |
FFMA.FTZ R7, R7, R4, c[0x2][0x10]; // | 1 : | 10
::::v::x:: | 1 : |
FMUL.FTZ R4, R7, R4; // | 1 : | 10
::::x::v:: | 1 : |
IMAD.HI.X R7, R3, R8, c[0x0][0x14c]; // | 1 v | 10
:::v:::^v: | 1 : |
FFMA.FTZ R4, R4, R5, R5; // | | 10
::::xv:::: | 1 : |
IADD R3, R3, R0; // | | 9 v::x:
:::: | 1 : |
FADD32I.FTZ R5, -R4, 1.5707963705062866211; // | | 10
::::v^:::: | 1 : |
@P0 FADD.FTZ R5, R4, R4; // | | 10
::::v^:::: | 1 v |
ISETP.LT.AND P0, PT, R3, c[0x0][0x150], PT; // | | 9 :::v
::::: | 1 ^ |
FADD32I.FTZ R4, -R5, 3.1415927410125732422; // | | 10
::::^v:::: | 1 : |
FCMP.LT.FTZ R2, R4, R5, R2; // | | 10
::x:vv:::: | 1 : |
ST.E [R6], R2; // | | 8 ::v:
vv:: | 1 : |
@P0 BRA `(.L_1); // | | 5 :: :
:: | 1 v |
MOV RZ, RZ; // | | 1 :
| |
EXIT; // | | 1 :
| |
//
+......+...............+.....+
BRA `(.L_2); // | |
| |
//
+------+---------------+-----+
// Legend:
// ^ :
Register assignment
// v :
Register usage
// x :
Register usage and reassignment
// : :
Register in use
// <space> :
Register not in use
// # :
Number of occupied registers
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