[llvm-bugs] [Bug 39464] New: __builtin_ia32_addcarry_u64 produces better code then __builtin_addcll.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=39464

            Bug ID: 39464
           Summary: __builtin_ia32_addcarry_u64 produces better code then
                    __builtin_addcll.
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: ilya.lesokhin at gmail.com
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org

When __builtin_ia32_addcarry_u64  is used the compiler is able to take
advantage of the ADC command to do carry propagation.

But it is unable to do so with __builtin_addcll.

https://godbolt.org/z/UQTOJX

compiling 
#define N 3
auto add_ia32 (const std::array<uint64_t, N> &a, const std::array<uint64_t, N>
&b)
{
    uint64_t carry = 0;
    std::array<uint64_t, N> r;

     for (int i = 0; i < N; ++i) {
      carry = __builtin_ia32_addcarry_u64(carry, a[i], b[i], (unsigned long
long *)&r[i]);
    }

    return r;
}
results in:
  movq %rdi, %rax
  movq (%rsi), %rcx
  xorl %edi, %edi
  addb $-1, %dil
  adcq (%rdx), %rcx
  movq %rcx, (%rax)
  movq 8(%rsi), %rcx
  adcq 8(%rdx), %rcx
  movq %rcx, 8(%rax)
  movq 16(%rsi), %rcx
  adcq 16(%rdx), %rcx
  movq %rcx, 16(%rax)
  retq

while
#define N 3
auto add_builtin (const std::array<uint64_t, N> &a, const std::array<uint64_t,
N> &b)
{
    unsigned long long carry = 0;
    std::array<uint64_t, N> r;

     for (int i = 0; i < N; ++i) {
       r[i] = __builtin_addcll(a[i], b[i], carry, &carry);
    }

    return r;
}

results in: 
  movq %rdi, %rax
  movq (%rsi), %rcx
  movq (%rdx), %r8
  leaq (%rcx,%r8), %rdi
  movq %rdi, (%rax)
  movq 8(%rsi), %rdi
  addq 8(%rdx), %rdi
  setb %r9b
  addq %r8, %rcx
  adcq $0, %rdi
  setb %cl
  orb %r9b, %cl
  movzbl %cl, %ecx
  movq %rdi, 8(%rax)
  movq 16(%rsi), %rsi
  addq 16(%rdx), %rsi
  addq %rcx, %rsi
  movq %rsi, 16(%rax)

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