[llvm-bugs] [Bug 39300] New: [AMDGPU][MC] Many MIMG opcodes do not accept tfe with dmask:0xf

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=39300

            Bug ID: 39300
           Summary: [AMDGPU][MC] Many MIMG opcodes do not accept tfe with
                    dmask:0xf
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

The reason for this issue is that current implementation does not support
5-register tuples.

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