[llvm-bugs] [Bug 36951] [X86] SandyBridge/Haswell/Broadwell/Skylake scheduler models lose the ReadAdvance information for all instructions that load from memory and read another operand from a register

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36951

Simon Pilgrim <llvm-dev at redking.me.uk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #1 from Simon Pilgrim <llvm-dev at redking.me.uk> ---
Works in trunk - added test case at rL343795

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