[llvm-bugs] [Bug 37563] New: [llvm-exegesis] Latency varies depending on selected register.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=37563

            Bug ID: 37563
           Summary: [llvm-exegesis] Latency varies depending on selected
                    register.
           Product: new-bugs
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: courbet at google.com
                CC: llvm-bugs at lists.llvm.org

./bin/llvm-exegesis -mode=latency -opcode-name=MPSADBWrri

has latency 7 or 6 depending on the time of day.
We should select registers in a deterministic way for a given operand sequence
so that we can compare instructions together (for example, right now alalysis
find inconsistencies between VMPSADBWrri and MPSADBWrri but they are the same).

This is orthogonal to exploring the register assignments and/or values).


---
key:             
  opcode_name:     MPSADBWrri
  mode:            latency
  config:          ''
cpu_name:        haswell
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:    
  - { key: latency, value: 7.0057, debug_string: '' }
error:           ''
info:            'explicit self cycles, selecting one aliasing configuration.
Snippet:
MPSADBWrri XMM11, XMM11, XMM11, 1
'
...

---
key:             
  opcode_name:     MPSADBWrri
  mode:            latency
  config:          ''
cpu_name:        haswell
llvm_triple:     x86_64-unknown-linux-gnu
num_repetitions: 10000
measurements:    
  - { key: latency, value: 6.0057, debug_string: '' }
error:           ''
info:            'explicit self cycles, selecting one aliasing configuration.
Snippet:
MPSADBWrri XMM15, XMM15, XMM13, 1
'
...

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