[llvm-bugs] [Bug 37402] [inline asm, AVX] Issue with the SSE register allocation in inline assembly

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=37402

Raphael Bost <raphael_bost at alumni.brown.edu> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |INVALID

--- Comment #5 from Raphael Bost <raphael_bost at alumni.brown.edu> ---
Well, I had taken a look at this page
https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html, and I understood the
paragraph about the '&' modifier completely differently (and I was not the only
one around me :). But now, it totally makes sense.


For the record, the part of the doc Craig mentioned is there:
https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#OutputOperands

Thanks Craig, 
And sorry for the false alarm.

(In reply to Craig Topper from comment #4)
> I'll admit I'm not great with inline assembly rules, but don't you need to
> put an '&' in the output constraint for vc in Implementation 1.
> 
> From gcc docs
> 
> "Use the ‘&’ constraint modifier (see Modifiers) on all output operands that
> must not overlap an input. Otherwise, GCC may allocate the output operand in
> the same register as an unrelated input operand, on the assumption that the
> assembler code consumes its inputs before producing outputs. This assumption
> may be false if the assembler code actually consists of more than one
> instruction."

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20180510/fc651620/attachment.html>