[llvm-bugs] [Bug 36666] New: [llvm-mca] [Scheduling Model] Let models optionally specify which buffered resources are load/store queues.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36666

            Bug ID: 36666
           Summary: [llvm-mca] [Scheduling Model] Let models optionally
                    specify which buffered resources are load/store
                    queues.
           Product: new-bugs
           Version: unspecified
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: andrea.dibiagio at gmail.com
                CC: llvm-bugs at lists.llvm.org

llvm-mca simulates the load/store queue differently from other functional
units. In particular, class LSUnit.h emulates a load/store unit implementing
queues for speculative execution of loads and stores.

At the moment, llvm-mca assumes a global LSUnit with a single load queue and a
single store queue.
However, there is no way currently in the LLVM model to tell which buffered
resources are modeling load queues (or store queues).
So, the tool optimistically assumes that the nuber of slots in the load/store
queues is unbounded.

Users can specify flag -lqueue=<uint> (vic. -squeue=<uint>) to override the
size of the load (vic. store) queue. However, it would be nice to to obtain
that information directly from the scheduling model.

The goal is to let models to (optionally) specify buffered resources are
load/store queue. By design, the tool expects a single load queue and a single
store queue (this may change in future). This may require extra checks in the
tablegen verifier functions.

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