[llvm-bugs] [Bug 36018] New: [GlobalISel][AArch64] Two load instructions generated for single volatile load

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36018

            Bug ID: 36018
           Summary: [GlobalISel][AArch64] Two load instructions generated
                    for single volatile load
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: GlobalISel
          Assignee: unassignedbugs at nondot.org
          Reporter: john.brawn.123 at gmail.com
                CC: llvm-bugs at lists.llvm.org

For the following IR:

  @g = global i16 0, align 2
  declare void @bar(i32)

  define hidden void @foo() {
    %1 = load volatile i16, i16* @g, align 2
    %2 = sext i16 %1 to i32
    call void @bar(i32 %2)
    ret void
  }

llc -mtriple=aarch64 -global-isel generates for the load followed by sext:

  adrp  x8, g
  add   x8, x8, :lo12:g
  ldrh  wzr, [x8]
  ldrsh w0, [x8]

g is loaded twice, once with a zero-extending load which is discarded, and
second with a sign-extending load. For a volatile load we should be generating
only a single load instruction.

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