[llvm-bugs] [Bug 35956] New: [X86] Scheduler information for FXRSTOR on Sandybridge looks bogus

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=35956

            Bug ID: 35956
           Summary: [X86] Scheduler information for FXRSTOR on Sandybridge
                    looks bogus
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: craig.topper at gmail.com
                CC: llvm-bugs at lists.llvm.org

I highly doubt this is correct. Every other scheduler model shows an order of
magnitude more uops and instructions.

def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
  let Latency = 5;
  let NumMicroOps = 5;
  let ResourceCycles = [1,2,1,1];
}
def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;

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