[llvm-bugs] [Bug 36354] New: [x86] x86 DAG->DAG Instruction Selection ignores connections between MXCSR operations and intrinsics

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=36354

            Bug ID: 36354
           Summary: [x86] x86 DAG->DAG Instruction Selection ignores
                    connections between MXCSR operations and intrinsics
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: ilia.taraban at intel.com
                CC: llvm-bugs at lists.llvm.org

This test exits with wrong result after x86 DAG->DAG Instruction Selection

================= without-store.ll ==============
target triple = "x86_64-unknown-linux-gnu"

@a = global <4 x i1> zeroinitializer

; Function Attrs: nounwind uwtable
define i32 @main() #0 {
  %1 = alloca i32, align 4
  %2 = bitcast i32* %1 to i8*
  call void @llvm.x86.sse.stmxcsr(i8* %2)
  %3 = load i32, i32* %1, align 4
  %4 = and i32 %3, -64
  %5 = or i32 %4, 62
  store i32 %5, i32* %1, align 4
  call void @llvm.x86.sse.ldmxcsr(i8* %2)
  %6 = call <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double>  <double
0.0, double 0.0, double 0.0, double 0x7FF8000000000000>, <4 x double> <double
0.0, double 0.0, double 0.0, double 0.0>, i32 1)
  call void @llvm.x86.sse.stmxcsr(i8* %2)
  %7 = load i32, i32* %1, align 4
  %8 = and i32 %7, 1
  ;store <4 x i1> %6, <4 x i1>* @a
  ret i32 %8
}

; Function Attrs: nounwind
declare void @llvm.x86.sse.stmxcsr(i8*) #1

; Function Attrs: nounwind
declare void @llvm.x86.sse.ldmxcsr(i8*) #1

; Function Attrs: nounwind readnone
declare <4 x i1> @llvm.x86.avx512.mask.cmp.pd.256(<4 x double>, <4 x double>,
i32) #2

attributes #0 = { nounwind uwtable "target-cpu"="skx" }
attributes #1 = { nounwind }
attributes #2 = { nounwind readnone }
=================================================

This test should return 1, because of NaN(0x7FF8000000000000) in
llvm.x86.avx512.mask.cmp.pd.256.
But it returns 0.

>>> clang -v
clang version 7.0.0 (trunk 324869)
Target: x86_64-unknown-linux-gnu
Thread model: posix
...


>>> clang without-store.ll
>>> ./a.out
0


Let's look at without-store asm:


================= without-store.s ==============
main:                                   # @main
        .cfi_startproc
# %bb.0:
        vstmxcsr        -4(%rsp)
        movl    -4(%rsp), %eax
        andl    $-64, %eax
        orl     $62, %eax
        movl    %eax, -4(%rsp)
        vldmxcsr        -4(%rsp)
        vstmxcsr        -4(%rsp)
        movl    -4(%rsp), %eax
        andl    $1, %eax
        retq
================================================

There is no "vcmpltpd" with nan argument.
Also if we uncomment "store" in our test, we'll receive same wrong result. But
now result is 0 because of wrong order of operations:

================= with-store.s ==============
main:                                   # @main
        .cfi_startproc
# %bb.0:
        vstmxcsr        -4(%rsp)
        movl    -4(%rsp), %eax
        andl    $-64, %eax
        orl     $62, %eax
        movl    %eax, -4(%rsp)
        vldmxcsr        -4(%rsp)
        vmovapd .LCPI0_0(%rip), %ymm0   # ymm0 =
[0.000000e+00,0.000000e+00,0.000000e+00,nan]
        vstmxcsr        -4(%rsp)
        vxorpd  %xmm1, %xmm1, %xmm1
        vcmpltpd        %ymm1, %ymm0, %k0
        movl    -4(%rsp), %eax
        andl    $1, %eax
        kmovb   %k0, a(%rip)
        vzeroupper
        retq
=============================================

Only if we change manually order of operations to "vstmxcsr" - "vldmxcsr" -
"vcmpltpd" - "vstmxcsr", we'll catch _MM_EXCEPT_INVALID exception.

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