[llvm-bugs] [Bug 40142] New: pmuludq may generate an explicit mask beforehand.

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=40142

            Bug ID: 40142
           Summary: pmuludq may generate an explicit mask beforehand.
           Product: libraries
           Version: 7.0
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: husseydevin at gmail.com
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org,
                    llvm-dev at redking.me.uk, spatel+llvm at rotateright.com

This is a regression in 7.0.0.

I was trying to mess with multiply code for SSE, and found that Clang
7.0.0-trunk (regression from 6) will do an explicit mask occasionally before a
pmuludq. This results in either a pand or a pblendq, depending on whether
SSE4.1 is enabled.

This is obviously redundant, as pmuludq clears the odd lanes automatically.

This C code:

    #include <emmintrin.h>

    __m128i pmuludq_square(__m128i val)
    {
        return _mm_mul_epu32(val, val);
    }

with -O3, optimizes to this.

    U64x2 pmuludq_square(U64x2 val)
    {
    #ifdef __SSE4_1__
        const U32x4 mask = { 0, 0, 0, 0 };
        val = (U64x2)__builtin_shufflevector((U32x4)val, mask, 0, 4, 2, 4);
    #else
        const U64x2 mask = { 0xFFFFFFFF, 0xFFFFFFFF };
        val &= mask;
    #endif
        return _mm_mul_epu32(val, val);
    }

https://godbolt.org/z/47NWxr

LLVM code:

    define <2 x i64> @pmuludq_square(<2 x i64> %val)
    {
        %v32 = bitcast <2 x i64> %val to <4 x i32>
        %mul = tail call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %v32, <4 x
i32> %v32)
        ret <2 x i64> %mul
    }

    declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) #1

opt -O3:

    define <2 x i64> @pmuludq_square(<2 x i64> %val) local_unnamed_addr #0 {
        %1 = and <2 x i64> %val, <i64 4294967295, i64 4294967295>
        %2 = mul nuw <2 x i64> %1, %1
        ret <2 x i64> %2
    }

https://godbolt.org/z/qTc2Zg

Related to bug 40032.

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