[llvm-bugs] [Bug 39983] New: [Hexagon] crash: failed to select v2i16 shift op

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=39983

            Bug ID: 39983
           Summary: [Hexagon] crash: failed to select v2i16 shift op
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: Hexagon
          Assignee: unassignedbugs at nondot.org
          Reporter: spatel+llvm at rotateright.com
                CC: llvm-bugs at lists.llvm.org

I'm working on a generic DAGCombiner transform and hit this Hexagon backend
crash which looks to be an independent bug. This test is reduced from
test/CodeGen/Hexagon/vect/vect-vaslw.ll:

target datalayout =
"e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon-unknown-linux-gnu"

define <2 x i16> @foo(<2 x i32>* nocapture %v) nounwind {
  %vec = load <2 x i32>, <2 x i32>* %v, align 2
  %trunc = trunc <2 x i32> %vec to <2 x i16>
  %r = lshr <2 x i16> %trunc, <i16 4, i16 4>
  ret <2 x i16> %r
}

$ llc -o - vect-vaslw.ll 
        .text
        .file   "vect-vaslw.ll"
LLVM ERROR: Cannot select: t14: v2i16 = HexagonISD::VLSR t6, Constant:i32<4>
  t6: v2i16 = truncate t16
    t16: v2i32 = bitcast t23
      t23: i64 = or t22, t29
        t22: i64 = shl t48, Constant:i32<32>
          t48: i64 = any_extend t43
            t43: i32 = or t42, t39
              t42: i32 = shl t41, Constant:i32<16>
                t41: i32,ch = load<(load 2 from %ir.v + 6), zext from i16> t0,
t47, undef:i32
                  t47: i32 = add t2, Constant:i32<6>

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