[llvm-bugs] [Bug 39855] New: zext inhibits shl+and+shr optimization

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=39855

            Bug ID: 39855
           Summary: zext inhibits shl+and+shr optimization
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: nikita.ppv at gmail.com
                CC: llvm-bugs at lists.llvm.org

For

define i128 @test([4 x i128]* %table, i32 %idx) {
  %a = lshr i32 %idx, 4
  %b = and i32 %a, 3
  %c = zext i32 %b to i64
  %d = getelementptr inbounds [4 x i128], [4 x i128]* %table, i64 0, i64 %c
  %r = load i128, i128* %d, align 8
  ret i128 %r
}

llc generates:

        shrl    $4, %esi
        andl    $3, %esi
        shlq    $4, %rsi
        movq    (%rdi,%rsi), %rax
        movq    8(%rdi,%rsi), %rdx
        retq

Doing the same without the zext

define i128 @test([4 x i128]* %table, i64 %idx) {
  %a = lshr i64 %idx, 4
  %b = and i64 %a, 3
  %d = getelementptr inbounds [4 x i128], [4 x i128]* %table, i64 0, i64 %b
  %r = load i128, i128* %d, align 8
  ret i128 %r
}

results in

        andl    $48, %esi
        movq    (%rdi,%rsi), %rax
        movq    8(%rdi,%rsi), %rdx
        retq

which is the desired output.

This combine is carried out by
https://github.com/llvm-mirror/llvm/blob/d1c472605b0ff640ff202a7faee1fc3dad0174b6/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L6177,
which is able to handle a (shl (and (sra))) chain, but not (shl (zext (and
(sra)))).

Rust bug report: https://github.com/rust-lang/rust/issues/56057

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