[llvm-bugs] [Bug 37269] New: [AArch64] Improve FNEG DAGCombine: (fneg (fmul c, x)) -> (fmul -c, x) on AArch64
via llvm-bugs
llvm-bugs at lists.llvm.org
Fri Apr 27 06:46:00 PDT 2018
https://bugs.llvm.org/show_bug.cgi?id=37269
Bug ID: 37269
Summary: [AArch64] Improve FNEG DAGCombine: (fneg (fmul c, x))
-> (fmul -c, x) on AArch64
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: Backend: AArch64
Assignee: unassignedbugs at nondot.org
Reporter: mcrosier at codeaurora.org
CC: llvm-bugs at lists.llvm.org
The generic DAG combiner has the following rule in visitFNEG:
(fneg (fmul c, x)) -> (fmul -c, x)
Given the following C code:
void t1(double a, double *ptr) {
double b = 0.5 * a;
ptr[0] = b;
ptr[1] = -b;
}
Clang will generate the following assembly for AArch64 (with -O3
-ffp-contract=fast):
t1:
fmov d1, #0.50000000
fmov d2, #-0.50000000
fmul d1, d0, d1
fmul d0, d0, d2
stp d1, d0, [x0]
ret
I can think of two alternative code sequences.
Sequence 1:
t1:
fmov d1, #0.50000000
fmul d2, d0, d1
fnmul d0, d0, d1
stp d2, d0, [x0]
ret
Sequence 2:
t1:
fmov d1, #0.50000000
fmul d0, d0, d1
fneg d1, d0
stp d0, d1, [x0]
If we disable the aforementioned DAGCombine we'll get the first sequence. I
would expect this sequence to be strictly better, since an extra fmov is
removed (which is a result of the first fmul having multipled uses). GCC will
generate the code in sequence 2, but I haven't yet convinced myself this
sequence is better. Specifically, while the fneg may have a lower latency as
compared to a fmul or fnmul (at least this is the case on Falkor), the fneg
must wait for the first fmul to complete, thus I expect the critical path to be
longer.
FWIW, I wanted to record my findings, but I'm not currently pursuing this
issue.
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