[llvm-bugs] [Bug 24449] [x86] avoid big bad immediates in the instruction stream, part 3: merge stores

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=24449

Sanjay Patel <spatel+llvm at rotateright.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|NEW                         |RESOLVED

--- Comment #7 from Sanjay Patel <spatel+llvm at rotateright.com> ---
The non-zero case that might've escaped IR optimization should be fixed with:
https://reviews.llvm.org/rL313458

So we won't replace 2 scalar constant stores with 1 vector constant load + 1
vector store (and there's a corner case test for where it would likely have
been a win), but we should get cases where we know the vector ops reduce
instruction count.

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