[llvm-bugs] [Bug 35148] New: [AMDGPU][MC][GFX9][disassembler] incorrect default value of op_sel_hi for v_mad_mix*

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https://bugs.llvm.org/show_bug.cgi?id=35148

            Bug ID: 35148
           Summary: [AMDGPU][MC][GFX9][disassembler] incorrect default
                    value of op_sel_hi for v_mad_mix*
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: unassignedbugs at nondot.org
          Reporter: dpreobrazhensky at luxoft.com
                CC: llvm-bugs at lists.llvm.org

v_mad_mix* opcodes aren't really packed instructions.
They use op_sel and op_sel_hi in a different fashion than other VOP3P opcodes.

The most important difference from other VOP3P instructions is that the default
value of op_sel_hi bits is 0 rather than 1.

Currently disassembler does not account for this difference.

The following instruction is encoded as follows:

v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,1,1]
[0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]

However, disassembler decodes it incorrectly assuming that default value of
op_sel_hi is 0:

v_mad_mix_f32 v0, v1, v2, v3

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