[llvm-bugs] [Bug 35094] New: [AArch64] atomicrmw on Armv8.1-a can change memory ordering

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=35094

            Bug ID: 35094
           Summary: [AArch64] atomicrmw on Armv8.1-a can change memory
                    ordering
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: Christof.Douma at arm.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 19346
  --> https://bugs.llvm.org/attachment.cgi?id=19346&action=edit
example

The LD<OP>[A|L|AL] instructions in Armv8.1-a have different memory orderings if
the target register is the zero register (WZR or XZR). In particular they are
no longer loads if the target register is the zero register[1]. This means that
a load barrier ("fence acquire" in LLVM terms) will no longer order these
before the barrier.

These instructions are used for atomicrmw LLVM operations, and LLVM's "AArch64
Dead register definitions" pass tries to use the zero register. If it does, it
changes the semantics (memory order) of the program.

I don't have a real-life example. But I hope the attached example makes the
story a bit clearer.

[1] Arm ARM for Armv8-A [ARM DDI 0487B.b] section C3.2.13
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0487b.b/DDI0487B_b_armv8_arm.pdf
"The ST<OP> instructions, and LD<OP> instructions where the destination
register is WZR or XZR, are not regarded as doing a read for the purpose of a
DMB LD barrier."

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