[llvm-bugs] [Bug 35023] New: [arm] Assertion failed: (LiveCPSR && "CPSR liveness tracking is wrong!"), function UpdateCPSRUse, file lib/Target/ARM/Thumb2SizeReduction.cpp, line 961
via llvm-bugs
llvm-bugs at lists.llvm.org
Sat Oct 21 05:01:01 PDT 2017
https://bugs.llvm.org/show_bug.cgi?id=35023
Bug ID: 35023
Summary: [arm] Assertion failed: (LiveCPSR && "CPSR liveness
tracking is wrong!"), function UpdateCPSRUse, file
lib/Target/ARM/Thumb2SizeReduction.cpp, line 961
Product: new-bugs
Version: trunk
Hardware: PC
OS: All
Status: NEW
Severity: enhancement
Priority: P
Component: new bugs
Assignee: unassignedbugs at nondot.org
Reporter: dimitry at andric.com
CC: llvm-bugs at lists.llvm.org
As reported in https://bugs.freebsd.org/223072, recent versions of zstd cause
assertion errors (or "bad machine code" errors in old versions of clang), when
compiling one of its files.
The reduced test case becomes:
======================================================================
/* clang -cc1 -triple armv6kz -S -target-cpu arm1176jzf-s -O1
testcase-wrong-liveness.c */
typedef struct {
int a;
int b;
int c;
int d;
int e;
} f;
struct {
int format;
int g;
int h;
int i;
int j;
int k;
int l;
f m;
int n;
long long o;
int mtctx;
} p;
long long q;
void r();
void s() { r(p, p, q - 1); }
======================================================================
Recent versions of clang (after at least r307894) assert with:
======================================================================
Assertion failed: (LiveCPSR && "CPSR liveness tracking is wrong!"), function
UpdateCPSRUse, file
/share/dim/src/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp, line 961.
#0 0x00000000018a49b8 llvm::sys::PrintStackTrace(llvm::raw_ostream&)
(/share/dim/llvm/307894-trunk-freebsd12-amd64-ninja-rel-1/bin/clang+0x18a49b8)
#1 0x00000000018a4fa6 SignalHandler(int)
(/share/dim/llvm/307894-trunk-freebsd12-amd64-ninja-rel-1/bin/clang+0x18a4fa6)
#2 0x0000000804330946 handle_signal /usr/src/lib/libthr/thread/thr_sig.c:0:3
Stack dump:
0. Program arguments:
/share/dim/llvm/307894-trunk-freebsd12-amd64-ninja-rel-1/bin/clang -cc1 -triple
armv6kz--freebsd12.0-gnueabihf -S -target-cpu arm1176jzf-s -target-feature
+strict-align -target-abi aapcs-linux -mfloat-abi hard -O2 testcase.c
1. <eof> parser at end of file
2. Code generation
3. Running pass 'Function Pass Manager' on module 'testcase.c'.
4. Running pass 'Thumb2 instruction size reduction pass' on function '@s'
Abort trap
======================================================================
Older versions (before at least r305575) crash with a long machine code dump,
and finally "Bad machine code: Using an undefined physical register":
======================================================================
# In Register Scavenger
# Machine code for function s: NoPHIs, TracksLiveness, NoVRegs
Frame Objects:
fi#0: size=4, align=4, at location [SP-4]
fi#1: size=4, align=4, at location [SP-8]
fi#2: size=4, align=4, at location [SP-12]
fi#3: size=4, align=4, at location [SP-16]
fi#4: size=4, align=4, at location [SP-20]
fi#5: size=4, align=4, at location [SP-24]
Constant Pool:
cp#0: q(GOT_PREL)-(LPC1+8-.), align=4
cp#1: p(GOT_PREL)-(LPC0+8-.), align=4
cp#2: 72, align=4
BB#0: derived from LLVM BB %entry
Live Ins: %R5 %R6 %R7 %R8 %R9 %LR
%SP<def,tied1> = STMDB_UPD %SP<tied0>, pred:14, pred:%noreg, %R5<kill>,
%R6<kill>, %R7<kill>, %R8<kill>, %R9<kill>, %LR<kill>; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
%SP<def> = SUBri %SP<kill>, 136, pred:14, pred:%noreg, opt:%noreg;
flags: FrameSetup
CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
%R0<def> = LDRi12 <cp#0>, 0, pred:14, pred:%noreg;
mem:LD4[ConstantPool]
%R1<def> = LDRi12 <cp#1>, 0, pred:14, pred:%noreg;
mem:LD4[ConstantPool]
%R0<def> = PICLDR %R0<kill>, 1, pred:14, pred:%noreg; mem:LD4[GOT]
%LR<def> = PICLDR %R1<kill>, 0, pred:14, pred:%noreg; mem:LD4[GOT]
%R8<def>, %R9<def> = LDRD %R0<kill>, %noreg, 0, pred:14, pred:%noreg;
mem:LD4[@q](align=8)(tbaa=!4)(dereferenceable)
LD4[@q+4](tbaa=!4)(dereferenceable)
%R7<def> = ADDri %LR, 16, pred:14, pred:%noreg, opt:%noreg
%R0<def> = LDRi12 %LR, 0, pred:14, pred:%noreg;
mem:LD4[<unknown>](align=8)
%R1<def> = LDRi12 %LR, 4, pred:14, pred:%noreg; mem:LD4[<unknown>]
%R2<def> = LDRi12 %LR, 8, pred:14, pred:%noreg;
mem:LD4[<unknown>](align=8)
%R3<def> = LDRi12 %LR, 12, pred:14, pred:%noreg; mem:LD4[<unknown>]
%R12<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<def> = COPY %SP
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R12<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R6<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R6<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R5<def>, %R7<def,dead,tied2> = LDR_POST_IMM %R7<kill,tied1>, %noreg,
4, pred:14, pred:%noreg
%R6<earlyclobber,def,dead,tied2> = STR_POST_IMM %R5<kill>,
%R6<kill,tied0>, %noreg, 4, pred:14, pred:%noreg
%R7<def> = SUBri %R8<kill>, 1, pred:14, pred:%noreg,
opt:%CPSR<def,dead>
STRi12 %R7<kill>, %SP, 128, pred:14, pred:%noreg; mem:ST4[Stack+128]
%R7<def> = ADDri %SP, 56, pred:14, pred:%noreg, opt:%noreg
%R6<def> = LDRcp <cp#2>, 0, pred:14, pred:%noreg
Successors according to CFG: BB#1(?%)
BB#1: derived from LLVM BB %entry
Live Ins: %LR %R0 %R1 %R2 %R3 %R6 %R7 %R9
Predecessors according to CFG: BB#0 BB#1
%R5<def>, %LR<def,tied2> = LDR_POST_IMM %LR<kill,tied1>, %noreg, 4,
pred:14, pred:%noreg
%R7<earlyclobber,def,tied2> = STR_POST_IMM %R5<kill>, %R7<kill,tied0>,
%noreg, 4, pred:14, pred:%noreg
%R6<def> = SUBri %R6<kill>, 4, pred:14, pred:%noreg, opt:%CPSR<def>
Bcc <BB#1>, pred:1, pred:%CPSR<kill>
Successors according to CFG: BB#1(?%) BB#2(?%)
BB#2: derived from LLVM BB %entry
Live Ins: %R0 %R1 %R2 %R3 %R9
Predecessors according to CFG: BB#1
%R7<def> = SBCri %R9<kill>, 0, pred:14, pred:%noreg, opt:%noreg,
%CPSR<imp-use,kill>
STRi12 %R7<kill>, %SP, 132, pred:14, pred:%noreg; mem:ST4[Stack+132]
BL <ga:@r>, <regmask %LR %D8 %D9 %D10 %D11 %D12 %D13 %D14 %D15 %Q4 %Q5
%Q6 %Q7 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R11 %S16 %S17 %S18 %S19 %S20 %S21 %S22
%S23 %S24 %S25 %S26 %S27 %S28 %S29 %S30 %S31 %D8_D10 %D9_D11 %D10_D12 %D11_D13
%D12_D14 %D13_D15 %Q4_Q5 %Q5_Q6 %Q6_Q7 %Q4_Q5_Q6_Q7 %R4_R5 %R6_R7 %R8_R9
%R10_R11 %D8_D9_D10 %D9_D10_D11 %D10_D11_D12 %D11_D12_D13 %D12_D13_D14
%D13_D14_D15 %D8_D10_D12 %D9_D11_D13 %D10_D12_D14 %D11_D13_D15 %D8_D10_D12_D14
%D9_D11_D13_D15 %D9_D10 %D11_D12 %D13_D14 %D9_D10_D11_D12 %D11_D12_D13_D14>,
%LR<imp-def,dead>, %SP<imp-use>, %R0<imp-use>, %R1<imp-use>, %R2<imp-use>,
%R3<imp-use>, %SP<imp-def>
%SP<def> = ADDri %SP<kill>, 136, pred:14, pred:%noreg, opt:%noreg
%SP<def,tied1> = LDMIA_RET %SP<tied0>, pred:14, pred:%noreg, %R5<def>,
%R6<def>, %R7<def>, %R8<def>, %R9<def>, %PC<def>
# End machine code for function s.
*** Bad machine code: Using an undefined physical register ***
- function: s
- basic block: BB#2 entry (0x2ce15ec4)
- instruction: %R7<def> = SBCri
- operand 6: %CPSR<imp-use,kill>
fatal error: error in backend: Found 1 machine code errors.
======================================================================
--
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20171021/bf011617/attachment.html>
More information about the llvm-bugs
mailing list