[llvm-bugs] [Bug 34924] New: Remove 'zero shift' guards from rotation patterns

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=34924

            Bug ID: 34924
           Summary: Remove 'zero shift' guards from rotation patterns
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: davide at freebsd.org, efriedma at codeaurora.org,
                    llvm-bugs at lists.llvm.org, spatel+llvm at rotateright.com

For rotation patterns we often have code that prevents out of bounds shifts. 

Once we have created rotations its no longer necessary for these guards and
they should be removed to prevent pointless branches.

unsigned rotl(unsigned a, unsigned b) {
  return (b == 0 ? a : ((a >> (32-b)) | (a << b)));
}
unsigned rotr(unsigned a, unsigned b) {
  return (b == 0 ? a : ((a << (32-b)) | (a >> b)));
}

define i32 @rotl(i32, i32) {
  %3 = icmp eq i32 %1, 0
  br i1 %3, label %9, label %4

; <label>:4: ; preds = %2
  %5 = sub i32 32, %1
  %6 = lshr i32 %0, %5
  %7 = shl i32 %0, %1
  %8 = or i32 %6, %7
  br label %9

; <label>:9: ; preds = %2, %4
  %10 = phi i32 [ %8, %4 ], [ %0, %2 ]
  ret i32 %10
}

define i32 @rotr(i32, i32) {
  %3 = icmp eq i32 %1, 0
  br i1 %3, label %9, label %4

; <label>:4: ; preds = %2
  %5 = sub i32 32, %1
  %6 = shl i32 %0, %5
  %7 = lshr i32 %0, %1
  %8 = or i32 %6, %7
  br label %9

; <label>:9: ; preds = %2, %4
  %10 = phi i32 [ %8, %4 ], [ %0, %2 ]
  ret i32 %10
}

llc -mtriple=x86_64-unknown -mcpu=btver2

rotl:
        testl   %esi, %esi
        je      .LBB0_2
        movl    %esi, %ecx
        roll    %cl, %edi
.LBB0_2:
        movl    %edi, %eax
        retq

rotr:
        testl   %esi, %esi
        je      .LBB1_2
        movl    %esi, %ecx
        rorl    %cl, %edi
.LBB1_2:
        movl    %edi, %eax
        retq

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