[llvm-bugs] [Bug 33071] New: Assertion in register allocation on ARM

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=33071

            Bug ID: 33071
           Summary: Assertion in register allocation on ARM
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: yyc1992 at gmail.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 18454
  --> https://bugs.llvm.org/attachment.cgi?id=18454&action=edit
Test case

The IR attached causes an assertion in LLC on at least 3.9 and 4.0.

The failure is

```
llc:
/home/yuyichao/projects/julia/tests/master/deps/srccache/llvm-4.0.0/lib/CodeGen/VirtRegMap.cpp:443:
void {anonymous}::VirtRegRewriter::rewrite(): Assertion `PhysReg && "Invalid
SubReg for physical register"' failed.
```

Which is triggered on `%D16<def> = COPY %vreg29:ssub_0<kill>; DPR:%vreg29`.

Enclosing BB

```
400B    BB#1: derived from LLVM BB %if
            Live Ins: %R4 %R5 %R8 %R9 %S16
            Predecessors according to CFG: BB#0
416B            %D16<def> = FCONSTD 128, pred:14, pred:%noreg;
dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
432B            %D17<def> = VCVTDS %S16<kill>, pred:14, pred:%noreg;
dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
448B            %D16<def> = VADDD %D17<kill>, %D16<kill>, pred:14, pred:%noreg;
dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
464B            %R10<def>, %R7<def> = VMOVRRD %D16, pred:14, pred:%noreg;
dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
480B            %R0<def> = MOVi 1, pred:14, pred:%noreg, opt:%noreg
512B            %D16<def> = COPY %vreg29:ssub_0<kill>; DPR:%vreg29
560B            B <BB#4>;
dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
            Successors according to CFG: BB#4(?%)
```

Enclosing BB before `rewrite`

```
BB#1: derived from LLVM BB %if
    Live Ins: %R4 %R5 %R8 %R9 %S16
    Predecessors according to CFG: BB#0
        %vreg27<def> = FCONSTD 128, pred:14, pred:%noreg; DPR:%vreg27
dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
        %vreg28<def> = VCVTDS %vreg17<kill>, pred:14, pred:%noreg; DPR:%vreg28
SPR:%vreg17 dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
        %vreg29<def> = VADDD %vreg28<kill>, %vreg27<kill>, pred:14,
pred:%noreg; DPR:%vreg29,%vreg28,%vreg27
dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
        %vreg6<def>, %vreg5<def> = VMOVRRD %vreg29, pred:14, pred:%noreg;
GPR:%vreg6,%vreg5 DPR:%vreg29
dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
        %vreg72<def> = MOVi 1, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg72
        %vreg67<def> = COPY %vreg29:ssub_0<kill>; DPR:%vreg67,%vreg29
        B <BB#4>; dbg:/home/yuyichao/projects/julia/tests/master/script.jl:2
    Successors according to CFG: BB#4(?%)
```

Ref https://github.com/JuliaLang/julia/issues/21926

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