[llvm-bugs] [Bug 32481] New: SelectionDAGBuilder produces vector nodes without vector support (results in crash)
via llvm-bugs
llvm-bugs at lists.llvm.org
Thu Mar 30 23:48:32 PDT 2017
https://bugs.llvm.org/show_bug.cgi?id=32481
Bug ID: 32481
Summary: SelectionDAGBuilder produces vector nodes without
vector support (results in crash)
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: Common Code Generator Code
Assignee: unassignedbugs at nondot.org
Reporter: paulsson at linux.vnet.ibm.com
CC: llvm-bugs at lists.llvm.org
Created attachment 18201
--> https://bugs.llvm.org/attachment.cgi?id=18201&action=edit
reduced test case
A small test case that includes the type <1 x i8>, causes SelectionDAG to crash
on an older subtarget which does not have vector support.
Should this vector type with one element not be converted to i8 during
SelectionDAG construction, if the target has no vector support? Or is target
required to handle also these types of vector values regardless of vector
support?
Initial selection DAG: BB#1 'autogen_SD18500:CF244'
SelectionDAG has 24 nodes:
t0: ch = EntryToken
t16: f32 = ConstantFP<5.720826e-10>
t17: f32 = ConstantFP<1.107380e+14>
t18: ch = setune
t3: i1 = setcc undef:i1, undef:i1, setule:ch
t5: i32,ch = CopyFromReg t0, Register:i32 %vreg0
t7: i32 = AssertSext t5, ValueType:ch:i8
t8: i8 = truncate t7
t9: v1i8 = BUILD_VECTOR t8
t11: v1i8 = select t3, t9, undef:v1i8
t13: i32 = extract_vector_elt t11, Constant:i32<0>
t15: ch = CopyToReg t0, Register:i32 %vreg1, t13
t21: ch = brcond t15, Constant:i1<-1>, BasicBlock:ch<CF244 0x58627f8>
t23: ch = br t21, BasicBlock:ch<CF241.preheader 0x58628a8>
The SystemZ target then tries to emit an illegal truncate, as it was not
expecting this for zEC12.
Run with
bin/llc -mtriple=s390x-linux-gnu -mcpu=zEC12
(zEC12 is the previous version, which did not have vector support.)
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