[llvm-bugs] [Bug 32422] New: llvm-stress causes DAGCombiner to produce an illegal BUILD_VECTOR

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=32422

            Bug ID: 32422
           Summary: llvm-stress causes DAGCombiner to produce an illegal
                    BUILD_VECTOR
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: paulsson at linux.vnet.ibm.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 18170
  --> https://bugs.llvm.org/attachment.cgi?id=18170&action=edit
reduced llvm-stress test case

A nonsense function:

*** IR Dump After Module Verifier ***
define void @autogen_SD28844() #0 {
BB:
  %I = insertelement <8 x i8> zeroinitializer, i8 -95, i32 3
  %I8 = insertelement <8 x i8> zeroinitializer, i8 -119, i32 2
  %FC = uitofp <8 x i8> %I8 to <8 x float>
  %Cmp18 = fcmp uno <8 x float> zeroinitializer, %FC
  %I22 = insertelement <8 x i1> %Cmp18, i1 true, i32 5
  br label %CF

CF:                                               ; preds = %CF, %BB
  %Cmp40 = fcmp uno double 0xC663C682E9619F00, undef
  br i1 %Cmp40, label %CF, label %CF353

CF353:                                            ; preds = %CF
  %E195 = extractelement <8 x i1> %I22, i32 4
  ret void
}

causes ISel to crash:

DAGCombiner transforms

26: DAG.dump() = SelectionDAG has 10 nodes:
    t0: ch = EntryToken
        t64: v8i16 = BUILD_VECTOR Constant:i32<0>, Constant:i32<0>,
Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>,
Constant:i32<0>, Constant:i32<0>
      t66: v8i16 = sign_extend_inreg t64, ValueType:ch:v8i1
    t34: v8i16 = insert_vector_elt t66, Constant:i32<1>, Constant:i32<5>
  t19: ch = CopyToReg t0, Register:v8i16 %vreg0, t34

to

26: DAG.dump() = SelectionDAG has 8 nodes:
    t0: ch = EntryToken
      t76: v8i16 = BUILD_VECTOR Constant:i16<0>, Constant:i16<0>,
Constant:i16<0>, Constant:i16<0>, Constant:i16<0>, Constant:i16<0>,
Constant:i16<0>, Constant:i16<0>
    t34: v8i16 = insert_vector_elt t76, Constant:i32<1>, Constant:i32<5>
  t19: ch = CopyToReg t0, Register:v8i16 %vreg0, t34

, which later triggers (on BUILD_VECTOR)

/llvm/llvm-dev/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:921: void
{anonymous}::SelectionDAGLegalize::LegalizeOp(llvm::SDNode*): Assertion
`(TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
TargetLowering::TypeLegal || TLI.isTypeLegal(Op.getValueType()) ||
Op.getOpcode() == ISD::TargetConstant) && "Unexpected illegal type!"' failed.

This is because i16 is not a legal type on SystemZ, which means the
BUILD_VECTOR was transformed incorrectly. Could it be that the BUILD_VECTOR
should have TargetConstant operands, instead of Constant operands?

run with
bin/llc -mtriple=s390x-linux-gnu -mcpu=z13

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