[llvm-bugs] [Bug 33535] New: Scheduler breaks liveness info: No live segment at use / a subrange is not covered by the main range

via llvm-bugs llvm-bugs at lists.llvm.org
Tue Jun 20 15:49:43 PDT 2017


https://bugs.llvm.org/show_bug.cgi?id=33535

            Bug ID: 33535
           Summary: Scheduler breaks liveness info: No live segment at use
                    / a subrange is not covered by the main range
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: Matthew.Arsenault at amd.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 18675
  --> https://bugs.llvm.org/attachment.cgi?id=18675&action=edit
Testcase

# After Machine Instruction Scheduler
********** INTERVALS **********
EXEC_LO EMPTY
EXEC_HI EMPTY
SGPR96 EMPTY
SGPR97 EMPTY
SGPR98 EMPTY
SGPR99 EMPTY
SGPR101 EMPTY
%vreg21 [16r,48r:0)[48r,64r:1)[64r,80r:2)[80r,136r:3)  0 at 16r 1 at 48r 2 at 64r 3 at 80r
L00000001 [16r,136r:0)  0 at 16r L00000002 [48r,136r:0)  0 at 48r L00000004
[64r,136r:0)  0 at 64r L00000008 [80r,136r:0)  0 at 80r
%vreg24 [456r,472r:0)  0 at 456r
%vreg26 EMPTY
%vreg34 [304r,312r:0)  0 at 304r
%vreg35 [332r,416r:0)  0 at 332r
%vreg36 EMPTY
%vreg38 EMPTY
%vreg39 [168r,316r:0)  0 at 168r
%vreg40 [172r,424r:0)  0 at 172r
%vreg65 [316r,324r:0)  0 at 316r
%vreg72 [424r,432r:0)  0 at 424r
%vreg75 [312r,324r:0)  0 at 312r
%vreg76 [416r,432r:0)  0 at 416r
%vreg77 [128r,160B:0)[160B,324r:3)[324r,424r:1)[432r,544B:2)  0 at 128r 1 at 324r
2 at 432r 3 at 160B-phi L00000001 [128r,160B:0)[160B,316r:2)[324r,544B:1)  0 at 128r
1 at 324r 2 at 160B-phi L00000002 [128r,160B:0)[160B,424r:2)[432r,544B:1)  0 at 128r
1 at 432r 2 at 160B-phi
%vreg78 [136r,160B:0)[160B,464r:1)[464r,472r:2)[472r,544B:3)  0 at 136r 1 at 160B-phi
2 at 464r 3 at 472r L00000008 [136r,160B:0)[160B,464r:1)[464r,544B:2)  0 at 136r
1 at 160B-phi 2 at 464r 3 at x L00000004 [136r,160B:0)[160B,472r:1)[472r,544B:2)  0 at 136r
1 at 160B-phi 2 at 472r L00000003 [136r,136d:0)  0 at 136r 1 at x 2 at x
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function no_live_segment_at_use: NoPHIs, TracksLiveness

0B      BB#0: derived from LLVM BB %entry
16B             %vreg21:sub0<def,read-undef> = S_MOV_B32 0; SReg_128:%vreg21
48B             %vreg21:sub1<def> = COPY %vreg21:sub0; SReg_128:%vreg21
64B             %vreg21:sub2<def> = COPY %vreg21:sub0; SReg_128:%vreg21
80B             %vreg21:sub3<def> = COPY %vreg21:sub0; SReg_128:%vreg21
128B            %vreg77<def> = IMPLICIT_DEF; VReg_64:%vreg77
136B            %vreg78<def> = COPY %vreg21; VReg_128:%vreg78 SReg_128:%vreg21
            Successors according to CFG: BB#1(?%)

160B    BB#1: derived from LLVM BB %do.body11.split
            Predecessors according to CFG: BB#0 BB#1
168B            %vreg39<def> = BUFFER_LOAD_DWORD_OFFSET
%SGPR96_SGPR97_SGPR98_SGPR99, %SGPR101, 0, 0, 0, 0, %EXEC<imp-use>;
mem:LD4[null](align=16) VGPR_32:%vreg39
172B            %vreg40<def> = BUFFER_LOAD_DWORD_OFFSET
%SGPR96_SGPR97_SGPR98_SGPR99, %SGPR101, 4, 0, 0, 0, %EXEC<imp-use>;
mem:LD4[null+4] VGPR_32:%vreg40
304B            %vreg34<def> = V_ALIGNBIT_B32 0, 0, 4, %EXEC<imp-use>;
VGPR_32:%vreg34
312B            %vreg75<def> = V_AND_B32_e32 %vreg34, %vreg39, %EXEC<imp-use>;
VGPR_32:%vreg75,%vreg34,%vreg39
316B            %vreg65<def> = V_XOR_B32_e32 %vreg77:sub0, %vreg39,
%EXEC<imp-use>; VGPR_32:%vreg65,%vreg39 VReg_64:%vreg77
324B            %vreg77:sub0<def> = V_XOR_B32_e32 %vreg65, %vreg75,
%EXEC<imp-use>; VReg_64:%vreg77 VGPR_32:%vreg65,%vreg75
332B            %vreg35<def> = V_ALIGNBIT_B32 %vreg36<undef>, %vreg38<undef>,
4, %EXEC<imp-use>; VGPR_32:%vreg35,%vreg38 SReg_32_XM0:%vreg36
416B            %vreg76<def> = V_AND_B32_e32 %vreg35, %vreg40, %EXEC<imp-use>;
VGPR_32:%vreg76,%vreg35,%vreg40
424B            %vreg72<def> = V_XOR_B32_e32 %vreg77:sub1, %vreg40,
%EXEC<imp-use>; VGPR_32:%vreg72,%vreg40 VReg_64:%vreg77
432B            %vreg77:sub1<def> = V_XOR_B32_e32 %vreg72, %vreg76,
%EXEC<imp-use>; VReg_64:%vreg77 VGPR_32:%vreg72,%vreg76
456B            %vreg24<def> = BUFFER_LOAD_DWORD_OFFEN %vreg26<undef>,
%SGPR96_SGPR97_SGPR98_SGPR99, %SGPR101, 0, 0, 0, 0, %EXEC<imp-use>;
mem:LD4[undef](align=32) VGPR_32:%vreg24,%vreg26
464B            %vreg78:sub3<def> = V_XOR_B32_e32 %vreg24, %vreg78:sub3,
%EXEC<imp-use>; VReg_128:%vreg78 VGPR_32:%vreg24
472B            %vreg78:sub2<def> = V_XOR_B32_e32 %vreg24, %vreg78:sub2,
%EXEC<imp-use>; VReg_128:%vreg78 VGPR_32:%vreg24
528B            S_BRANCH <BB#1>
            Successors according to CFG: BB#1(?%)

# End machine code for function no_live_segment_at_use.

*** Bad machine code: No live segment at use ***
- function:    no_live_segment_at_use
- basic block: BB#1 do.body11.split (0x5abdb48) [160B;544B)
- instruction: 432B     %vreg77:sub1<def> = V_XOR_B32_e32
- operand 0:   %vreg77:sub1<def>
- liverange:   [128r,160B:0)[160B,324r:3)[324r,424r:1)[432r,544B:2)  0 at 128r
1 at 324r 2 at 432r 3 at 160B-phi
- v. register: %vreg77
- at:          432B

*** Bad machine code: A Subrange is not covered by the main range ***
- function:    no_live_segment_at_use
- interval:    %vreg77 [128r,160B:0)[160B,324r:3)[324r,424r:1)[432r,544B:2) 
0 at 128r 1 at 324r 2 at 432r 3 at 160B-phi L00000001
[128r,160B:0)[160B,316r:2)[324r,544B:1)  0 at 128r 1 at 324r 2 at 160B-phi L00000002
[128r,160B:0)[160B,424r:2)[432r,544B:1)  0 at 128r 1 at 432r 2 at 160B-phi
LLVM ERROR: Found 2 machine code errors.

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