[llvm-bugs] [Bug 33743] New: DAG combiner asserts due to extend in-register size mismatch for shufflevector

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=33743

            Bug ID: 33743
           Summary: DAG combiner asserts due to extend in-register size
                    mismatch for shufflevector
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: david.stuttard at amd.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 18775
  --> https://bugs.llvm.org/attachment.cgi?id=18775&action=edit
Reproducer for shufflevec issue in DAGCombine

This issue has been seen when compiling for the AMDGPU backend

llc -march=amdgcn shufflevec-dagcombine-issue.ll

This results in the following assert:

Assertion failed: VT.getSizeInBits() == Op.getValueSizeInBits() && "The sizes
of the input and result must match in order to perform the " "extend
in-register.", file ~\llvm\lib\CodeGen\SelectionDAG\SelectionDAG.cpp, line 1012

This looks like an issue in combineShuffleToVectorExtend

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