[llvm-bugs] [Bug 35624] New: [X86] Missing UD1 and UD2 Opcodes

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https://bugs.llvm.org/show_bug.cgi?id=35624

            Bug ID: 35624
           Summary: [X86] Missing UD1 and UD2 Opcodes
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: craig.topper at gmail.com, llvm-bugs at lists.llvm.org

The AMD APM vol3 mentions UD0 and UD1 undefined opcodes as well as UD2:

UD0 0F FF Raise an invalid opcode exception
UD1 0F B9 /r Raise an invalid opcode exception
UD2 0F 0B Raise an invalid opcode exception.

We seem to support UD2, and UD1 is supported as the UD2B instruction (although
without the payload) but we don't seem to have anything that matches UD0.

The Intel docs only mention UD2.

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