[llvm-bugs] [Bug 34290] New: [AArch64] bad codegen for bitwise logic on vector of i1

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=34290

            Bug ID: 34290
           Summary: [AArch64] bad codegen for bitwise logic on vector of
                    i1
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: spatel+llvm at rotateright.com
                CC: llvm-bugs at lists.llvm.org

Taking this from:
https://reviews.llvm.org/D36213
...which will canonicalize IR to the 2nd form and potentially exacerbate the
existing problem. 

define <2 x i64> @test7(<4 x float> %a, <4 x float> %b) {
  %cmp = fcmp ult <4 x float> %a, zeroinitializer
  %cmp4 = fcmp ult <4 x float> %b, zeroinitializer
  %sext = sext <4 x i1> %cmp to <4 x i32>
  %sext5 = sext <4 x i1> %cmp4 to <4 x i32>
  %and = and <4 x i32> %sext, %sext5
  %conv = bitcast <4 x i32> %and to <2 x i64>
  ret <2 x i64> %conv
}

define <2 x i64> @test7_better_IR(<4 x float> %a, <4 x float> %b) {
  %cmp = fcmp ult <4 x float> %a, zeroinitializer
  %cmp4 = fcmp ult <4 x float> %b, zeroinitializer
  %and1 = and <4 x i1> %cmp, %cmp4
  %and = sext <4 x i1> %and1 to <4 x i32>
  %conv = bitcast <4 x i32> %and to <2 x i64>
  ret <2 x i64> %conv
}

$ ./llc -o - vcmp.ll -mtriple=aarch64

test7:                       
        fcmge   v0.4s, v0.4s, #0.0
        mvn      v0.16b, v0.16b
        fcmge   v1.4s, v1.4s, #0.0
        bic     v0.16b, v0.16b, v1.16b
        ret

test7_better_IR:                    
        fcmge   v0.4s, v0.4s, #0.0
        fcmge   v1.4s, v1.4s, #0.0
        mvn      v0.16b, v0.16b
        mvn      v1.16b, v1.16b
        xtn     v0.4h, v0.4s
        xtn     v1.4h, v1.4s
        and     v0.8b, v0.8b, v1.8b
        ushll   v0.4s, v0.4h, #0
        shl     v0.4s, v0.4s, #31
        sshr    v0.4s, v0.4s, #31
        ret

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