[llvm-bugs] [Bug 34225] New: 32bit ld instruction is generated for 64-bit addr load, sparc, segfault
via llvm-bugs
llvm-bugs at lists.llvm.org
Thu Aug 17 14:05:51 PDT 2017
https://bugs.llvm.org/show_bug.cgi?id=34225
Bug ID: 34225
Summary: 32bit ld instruction is generated for 64-bit addr
load, sparc, segfault
Product: new-bugs
Version: trunk
Hardware: Sun
OS: Solaris
Status: NEW
Severity: normal
Priority: P
Component: new bugs
Assignee: unassignedbugs at nondot.org
Reporter: alexander.kirov at oracle.com
CC: llvm-bugs at lists.llvm.org
Consider the code:
] cat reduced_inline_sparc.cpp
static volatile long max_hrtime = 0;
inline long cmpxchg(long exchange_value, volatile long* dest, long
compare_value) {
long rv;
__asm__ volatile(
" casx [%2], %3, %0"
: "=r" (rv)
: "0" (exchange_value), "r" (dest), "r" (compare_value)
: "memory");
return rv;
}
int main() {
const long now = max_hrtime;
const long prev = max_hrtime;
const long obsv = cmpxchg(now, (volatile long*)&max_hrtime, prev);
return 0;
}
] clang++ -m64 reduced_inline_sparc.cpp
] a.out
Segmentation Fault (core dumped)
If we consider instructions:
_Z7cmpxchglPVll+0x20: b0 16 20 04 or %i0, 0x4, %i0
_Z7cmpxchglPVll+0x24: f0 06 00 00 ld [%i0], %i0
_Z7cmpxchglPVll+0x28: b2 07 a7 ef add %fp, 0x7ef, %i1
_Z7cmpxchglPVll+0x2c: b2 16 60 04 or %i1, 0x4, %i1
_Z7cmpxchglPVll+0x30: f2 06 40 00 ld [%i1], %i1
_Z7cmpxchglPVll+0x34: b4 07 a7 e7 add %fp, 0x7e7, %i2
_Z7cmpxchglPVll+0x38: b4 16 a0 04 or %i2, 0x4, %i2
_Z7cmpxchglPVll+0x3c: f4 06 80 00 ld [%i2], %i2
_Z7cmpxchglPVll+0x40: f1 f6 50 1a casx [%i1], %i2, %i0
segfault happens on "casx [%i1]" call, when %i1 contains only 32 bits of the
64-bits long address, where maxhrtime is stored, as a result wrong address
constituted only by 32bits of the real address is referenced.
ld instrutions are used.
ldx instructions should be used.
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