[llvm-bugs] [Bug 32744] New: [X86][AVX1] Split 256-bit vector non-temporal loads to keep it non-temporal

via llvm-bugs llvm-bugs at lists.llvm.org
Sat Apr 22 08:29:32 PDT 2017


            Bug ID: 32744
           Summary: [X86][AVX1] Split 256-bit vector non-temporal loads to
                    keep it non-temporal
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: llvm-dev at redking.me.uk
                CC: llvm-bugs at lists.llvm.org, spatel+llvm at rotateright.com

SSE4.1 introduced 128-bit non-temporal loads and AVX2 introduced 256-bit
non-temporal loads.

But for AVX1 targets which have legal 256-bit vectors, we end up using 256-bit
temporal loads again - we need to split the 128-bit loads and concatenate the
results to prevent cache pollution.


define <8 x float> @test_v8f32(<8 x float>* %src) {
; SSE2-LABEL: test_v8f32:
; SSE2:       # BB#0:
; SSE2-NEXT:    movaps (%rdi), %xmm0
; SSE2-NEXT:    movaps 16(%rdi), %xmm1
; SSE2-NEXT:    retq
; SSE41-LABEL: test_v8f32:
; SSE41:       # BB#0:
; SSE41-NEXT:    movntdqa (%rdi), %xmm0
; SSE41-NEXT:    movntdqa 16(%rdi), %xmm1
; SSE41-NEXT:    retq
; AVX1-LABEL: test_v8f32:
; AVX1:       # BB#0:
; AVX1-NEXT:    vmovaps (%rdi), %ymm0
; AVX1-NEXT:    retq
; AVX2-LABEL: test_v8f32:
; AVX2:       # BB#0:
; AVX2-NEXT:    vmovntdqa (%rdi), %ymm0
; AVX2-NEXT:    retq
; AVX512-LABEL: test_v8f32:
; AVX512:       # BB#0:
; AVX512-NEXT:    vmovntdqa (%rdi), %ymm0
; AVX512-NEXT:    retq
  %1 = load <8 x float>, <8 x float>* %src, align 32, !nontemporal !1
  ret <8 x float> %1
!1 = !{i32 1}

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