[llvm-bugs] [Bug 32608] New: Post RA scheduler incorrectly renames callee saved register
via llvm-bugs
llvm-bugs at lists.llvm.org
Mon Apr 10 14:09:11 PDT 2017
https://bugs.llvm.org/show_bug.cgi?id=32608
Bug ID: 32608
Summary: Post RA scheduler incorrectly renames callee saved
register
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: ASSIGNED
Severity: enhancement
Priority: P
Component: Common Code Generator Code
Assignee: carrot at google.com
Reporter: carrot at google.com
CC: llvm-bugs at lists.llvm.org
Compile the following code with options
-fno-exceptions '-mcpu=power8' -O2 '-std=gnu++11'
class StringPiece {
public:
StringPiece(const char* data, int len): ptr_(data), length_(len) {}
int find(const char* s, int pos = 0);
const char* ptr_;
int length_;
};
bool foo(const char* hostname, int hostname_len) {
if (hostname_len <= 0)
return false;
const char* hostname_end = hostname + hostname_len;
if ((hostname_end[-1] == ' '))
return false;
if ((hostname[0] == '.') || (hostname_end[-2] == '.'))
return false;
if (hostname_len >= 4 && StringPiece(hostname, hostname_len).find("..", 0) !=
-1)
return false;
return true;
}
LLVM at revision r298955 generates following code for the later part of the
function
...
std 30, 48(1) # 8-byte Folded Spill
li 30, 0
addi 4, 3, .L.str at toc@l
addi 3, 1, 32
bl _ZN11StringPiece4findEPKci
nop
li 4, 1
cmpwi 0, 3, -1
ld 12, 48(1) # 8-byte Folded Reload
isel 3, 4, 30, 2
addi 1, 1, 64
ld 0, 16(1)
mtlr 0
blr
The instruction
ld 12, 48(1)
should be
ld 30, 48(1)
and moved after isel.
The problem can't be reproduced without patch r298955, but the bug is still
there.
The root cause is in post RA scheduler, llvm tries to break anti/output
dependence with register renaming. But for callee saved register restore
instruction, there is no explicit use of the register, simply rename the load
instruction can't restore the value of the register correctly.
We should not rename the callee saved register restore instruction.
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