[llvm-bugs] [Bug 30607] New: r283037 causes *** Bad machine code: Illegal virtual register for instruction ***

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=30607

            Bug ID: 30607
           Summary: r283037 causes *** Bad machine code: Illegal virtual
                    register for instruction ***
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: mikael.holmen at ericsson.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Created attachment 17399
  --> https://llvm.org/bugs/attachment.cgi?id=17399&action=edit
Reproducer

Running llc on the attached program makes the verifier complain since commit

r283037 - [X86][SSE] Enable commutation from MOVSD/MOVSS to BLENDPD/BLENDPS on
SSE41+ targets"

So

llc -march=x86-64 -mcpu=corei7 -o /dev/null red.ll -verify-coalescing

gives

# Before register coalescing
********** INTERVALS **********
%vreg0 [16r,176r:0)  0 at 16r
%vreg1 [32r,224r:0)  0 at 32r
%vreg2 [48r,192r:0)  0 at 48r
%vreg3 [176r,192r:0)[192r,208r:1)  0 at 176r 1 at 192r
%vreg5 [208r,224r:0)[224r,352r:1)  0 at 208r 1 at 224r
%vreg7 [64r,160B:0)  0 at 64r
%vreg8 EMPTY
%vreg9 [240r,336B:0)  0 at 240r
%vreg10 [272r,288r:0)  0 at 272r
%vreg11 EMPTY
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function autogen_SD17701: NoPHIs, TracksLiveness
Constant Pool:
  cp#0: 0x58C1C66036BF19DE, align=8

0B      BB#0: derived from LLVM BB %BB
16B             %vreg0<def> = V_SET0; VR128:%vreg0
32B             %vreg1<def> = COPY %vreg0; VR128:%vreg1,%vreg0
48B             %vreg2<def> = FsFLD0SD; FR64:%vreg2
64B             %vreg7<def> = MOVSDrm %RIP, 1, %noreg, <cp#0>, %noreg;
mem:LD8[ConstantPool] FR64:%vreg7
            Successors according to CFG: BB#1(?%)

80B     BB#1: derived from LLVM BB %CF248
            Predecessors according to CFG: BB#0 BB#1
96B             UCOMISDrr %vreg7, %vreg8<undef>, %EFLAGS<imp-def>;
FR64:%vreg7,%vreg8
112B            JNE_1 <BB#1>, %EFLAGS<imp-use>
128B            JNP_1 <BB#2>, %EFLAGS<imp-use,kill>
144B            JMP_1 <BB#1>
            Successors according to CFG: BB#1(0x7c000000 / 0x80000000 = 96.88%)
BB#2(0x04000000 / 0x80000000 = 3.12%)

160B    BB#2: derived from LLVM BB %CF251
            Predecessors according to CFG: BB#1
176B            %vreg3<def> = COPY %vreg0; VR128:%vreg3,%vreg0
192B            %vreg3<def,tied1> = BLENDPDrri %vreg3<tied0>, %vreg2, 1;
VR128:%vreg3 FR64:%vreg2
208B            %vreg5<def> = COPY %vreg3; VR128:%vreg5,%vreg3
224B            %vreg5<def,tied1> = UNPCKHPDrr %vreg5<tied0>, %vreg1;
VR128:%vreg5,%vreg1
240B            %vreg9<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg9
            Successors according to CFG: BB#3(?%)

256B    BB#3: derived from LLVM BB %CF265
            Predecessors according to CFG: BB#2 BB#3
272B            %vreg10<def> = COPY %vreg9:sub_8bit; GR8:%vreg10 GR32:%vreg9
288B            TEST8rr %vreg10, %vreg10, %EFLAGS<imp-def>; GR8:%vreg10
304B            JNE_1 <BB#3>, %EFLAGS<imp-use,kill>
320B            JMP_1 <BB#4>
            Successors according to CFG: BB#3(0x7ffff800 / 0x80000000 =
100.00%) BB#4(0x00000800 / 0x80000000 = 0.00%)

336B    BB#4: derived from LLVM BB %CF274
            Predecessors according to CFG: BB#3
352B            MOVHPDmr %vreg11<undef>, 1, %noreg, 0, %noreg, %vreg5;
mem:ST8[undef] GR64:%vreg11 VR128:%vreg5

# End machine code for function autogen_SD17701.

*** Bad machine code: Illegal virtual register for instruction ***
- function:    autogen_SD17701
- basic block: BB#2 CF251 (0x2d92358) [160B;256B)
- instruction: 192B     %vreg3<def,tied1> = BLENDPDrri
- operand 2:   %vreg2
Expected a VR128 register, but got a FR64 register
LLVM ERROR: Found 1 machine code errors.

The input was generated with llvm-stress and then bugpoint reduced.

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