[llvm-bugs] [Bug 30888] New: [AVX512DQ] v2i1/v4i1 stores should zero top bits

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=30888

            Bug ID: 30888
           Summary: [AVX512DQ] v2i1/v4i1 stores should zero top bits
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: cameron.mcinally at nyu.edu
                CC: elena.demikhovsky at intel.com, llvm-bugs at lists.llvm.org
    Classification: Unclassified

Created attachment 17543
  --> https://llvm.org/bugs/attachment.cgi?id=17543&action=edit
IR test case

Filing a Bug at Elena's request...

We're running into a problem with undefined top bits on masks less than 8b in
8b mask registers. The smallest mask register with AVX512DQ is 8 bits. And the
smallest mask load/store instruction moves 8b. Masks less than 8b (i.e. v2i1
and v4i1) are causing incorrect answers since the top bits are currently
undefined. 

>From what I’ve learnt on llvm-dev, LLVM expects the top bits of v2i1/v4i1 regs
to be zeroed upon stores. I’ve locally added a custom ISelLowering to achieve
this and that is functional, but produces a lot of KSHIFTs to clear the top
bits of the mask registers when the mask is < 8b.

  // Handle v2i1/v4i1 stores. LangRef assumes that
  // the undefined bits are zeroed. 
  EVT MemVT = St->getMemoryVT();
  SDValue Op = St->getValue();
  MVT OpVT = Op.getValueType().getSimpleVT();
  unsigned NumElts = OpVT.getVectorNumElements();
  if (MemVT.isVector() &&
      MemVT.getVectorElementType() == MVT::i1 &&
      NumElts <= 4) {
    Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1,
                     getZeroVector(MVT::v8i1, Subtarget, DAG, dl),
                     Op, DAG.getIntPtrConstant(0, dl));

    return DAG.getStore(St->getChain(), dl, Op, St->getBasePtr(),
                        St->getMemOperand());

And this produces code like:

        knotw   %k0, %k0                
        kshiftlb        $4, %k0, %k0    <-- These KSHIFTs are
        kshiftrb        $4, %k0, %k0    <-- zeroing the top bits.
        kmovb   %k0, 6(%rsp)            
        movzbl  6(%rsp), %ecx           
        kmovw   %ecx, %k0               
        kortestw        %k0, %k0        

The new KSHIFT instructions produce functional code, but this seems like a big
hammer. Can we do better?

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