[llvm-bugs] [Bug 27901] New: Invalid instructions generated for bitfield within a global structure.

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=27901

            Bug ID: 27901
           Summary: Invalid instructions generated for bitfield within a
                    global structure.
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PowerPC
          Assignee: unassignedbugs at nondot.org
          Reporter: iains-llvm at btconnect.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Created attachment 16425
  --> https://llvm.org/bugs/attachment.cgi?id=16425&action=edit
testcase .ll

For 32bit powerpc; for at least 3.8 and trunk. For Linux (no PIC) and for
Darwin (fPIC, -fno-common) invalid insns are generated

original c (reduced from a GCC ABI compatibility test) is;

cat reduced-t002.c:

enum E4 { e4_0, e4_1, e4_2, e4_3, e4_253 = 253, e4_254, e4_255 };

struct S482 {
  enum E4 a : 18;
  char b;
};

struct S482 s482;

void test482(void) {
    s482.a = e4_255;
}

====

Linux;
clang -target powerpc-gnu-linux reduced-t002.ll -fverbose-asm -save-temps -c
-mllvm -print-after-all

# *** IR Dump After Live DEBUG_VALUE analysis ***:
# Machine code for function test482: Post SSA
Frame Objects:
  fi#-1: size=4, align=4, fixed, at location [SP-4]

BB#0: derived from LLVM BB %entry
    STW %R31, -4, %R1
    %R1<def,tied3> = STWU %R1, -16, %R1<tied0>
    %R31<def> = OR %R1, %R1
    %R3<def> = ADDIS <ga:@s482>[TF=16], <ga:@s482>[TF=32]
    %R4<def> = LBZ 2, %R3; mem:LD1[bitcast (%struct.S482* @s482 to
i24*)+2](align=2)
    %R5<def> = LIS <ga:@s482>[TF=32]
    %R6<def> = LI 63
    %R4<def> = ORI %R4<kill>, 16320
    STHX %R6<kill>, %R5<kill>, <ga:@s482>[TF=16]; mem:ST2[bitcast
(%struct.S482* @s482 to i24*)](align=4)
    STB %R4<kill>, 2, %R3<kill>; mem:ST1[bitcast (%struct.S482* @s482 to
i24*)+2](align=2)
    %R1<def> = ADDI %R1, 16
    %R31<def> = LWZ -4, %R1
    BLR %LR<imp-use>, %RM<imp-use>

# End machine code for function test482.

reduced-t002.s:12:11: error: invalid operand for instruction
        addis 3, s482 at l, s482 at ha
                 ^
reduced-t002.s:17:13: error: invalid operand for instruction
        sthx 6, 5, s482 at l
                   ^

Darwin:
clang -target powerpc-apple-darwin reduced-t002.c -fno-common -fverbose-asm
-save-temps -c -mllvm -print-machineinstr

# After Live DEBUG_VALUE analysis:
# Machine code for function test482: Post SSA
Frame Objects:
  fi#-1: size=4, align=4, fixed, at location [SP-4]

BB#0: derived from LLVM BB %entry
    %R0<def> = MFLR %LR<imp-use>
    STW %R31, -4, %R1
    STW %R0, 8, %R1
    %R1<def,tied3> = STWU %R1, -32, %R1<tied0>
    %R31<def> = OR %R1, %R1
    MovePCtoLR %LR<imp-def>
    %R2<def> = MFLR %LR<imp-use>
    %R2<def> = ADDIS %R2<kill>, <ga:@s482>[TF=34]
    %R3<def> = ADD4 %R2, <ga:@s482>[TF=18]
    %R4<def> = LBZ 2, %R3; mem:LD1[bitcast (%struct.S482* @s482 to
i24*)+2](align=2)
    %R5<def> = LI 63
    %R4<def> = ORI %R4<kill>, 16320
    STHX %R5<kill>, %R2<kill>, <ga:@s482>[TF=18]; mem:ST2[bitcast
(%struct.S482* @s482 to i24*)](align=4)
    STB %R4<kill>, 2, %R3<kill>; mem:ST1[bitcast (%struct.S482* @s482 to
i24*)+2](align=2)
    %R1<def> = ADDI %R1, 32
    %R0<def> = LWZ 8, %R1
    %R31<def> = LWZ -4, %R1
    MTLR %R0, %LR<imp-def>
    BLR %LR<imp-use>, %RM<imp-use>

# End machine code for function test482.

reduced-t002.s:20:14: error: invalid operand for instruction
        add r3, r2, lo16(_s482-L0$pb)
                    ^
reduced-t002.s:24:15: error: invalid operand for instruction
        sthx r5, r2, lo16(_s482-L0$pb)
                     ^

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