[llvm-bugs] [Bug 27815] New: [AArch64] Combine loads of v4i8 to load of i32

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=27815

            Bug ID: 27815
           Summary: [AArch64] Combine loads of v4i8 to load of i32
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: junbuml at codeaurora.org
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

This is based on http://reviews.llvm.org/D20443.

In summary, for the test below,

define <16 x i8> @test(i32* %s, i32* %t) {
entry:
  %0 = bitcast i32* %s to <4 x i8>*
  %1 = load <4 x i8>, <4 x i8>* %0, align 4
  %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32
2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1,
i32 2, i32 3>
  ret <16 x i8> %2
}

AArch64 backend generates very inefficient code :

    ldrb        w8, [x0]
    ldrb    w9, [x0, #1]
    ldrb    w10, [x0, #2]
    ldrb    w11, [x0, #3]
    ins    v1.h[0], w8
    ins    v1.h[1], w9
    ins    v1.h[2], w10
    ins    v1.h[3], w11
    umov    w8, v1.h[0]
    umov    w9, v1.h[1]
    ins    v0.b[0], w8
    umov    w10, v1.h[2]
    ins    v0.b[1], w9
    ins    v0.b[2], w10
    umov    w11, v1.h[3]
    ins    v0.b[3], w11
    ins    v0.b[4], w8
    ins    v0.b[5], w9
    ins    v0.b[6], w10
    ins    v0.b[7], w11
    ins    v0.b[8], w8
    ins    v0.b[9], w9
    ins    v0.b[10], w10
    ins    v0.b[11], w11
    ins    v0.b[12], w8
    ins    v0.b[13], w9
    ins    v0.b[14], w10
    ins    v0.b[15], w11
    re

Like D20443, we can generate just like : 
  ld1r    { v0.4s }, [x0]

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