[llvm-bugs] [Bug 27143] New: [scheduler] memset stores don't occur from low-to-high addresses

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https://llvm.org/bugs/show_bug.cgi?id=27143

            Bug ID: 27143
           Summary: [scheduler] memset stores don't occur from low-to-high
                    addresses
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Common Code Generator Code
          Assignee: unassignedbugs at nondot.org
          Reporter: spatel+llvm at rotateright.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

This was noticed in the output of http://reviews.llvm.org/D18566 (bug 27100):

define void @store_32_bytes(i8* %x, i32 %v, i8 %c) {
  call void @llvm.memset.p0i8.i32(i8* %x, i8 42, i32 32, i32 1, i1 false)
  ret void
}

declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind

$ ./llc -o - memset.ll 
...
    movabsq    $3038287259199220266, %rax ## imm = 0x2A2A2A2A2A2A2A2A
    movq    %rax, 24(%rdi)
    movq    %rax, 16(%rdi)
    movq    %rax, 8(%rdi)
    movq    %rax, (%rdi)


The inverted order (high to low address offsets) of the stores from what was
created in the DAG suggests that the scheduler is doing unnecessary work with
no hope of any actual perf improvement. 

In the worst case, going backwards through memory might cause a perf regression
for simple HW that only detects forward accesses for prefetching.

This is not an x86-specific bug. I see the same behavior for PPC64 and AArch64.

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