[llvm-bugs] [Bug 28163] New: [mc] SOP2 u64/i64/u64 instructions -- source operands do not support floating inline constants

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https://llvm.org/bugs/show_bug.cgi?id=28163

            Bug ID: 28163
           Summary: [mc] SOP2 u64/i64/u64 instructions -- source operands
                    do not support floating inline constants
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AMDGPU
          Assignee: artem.tamazov at amd.com
          Reporter: artem.tamazov at amd.com
                CC: llvm-bugs at lists.llvm.org, nikolay.haustov at amd.com
    Classification: Unclassified

Created attachment 16564
  --> https://llvm.org/bugs/attachment.cgi?id=16564&action=edit
Failing lit1 tests

Example of failing instruction:
> s_mov_b64 s[0:1], 0.5

In the case above, 0.5 is encoded as 32-bit literal F32 constant (0x3f000000),
which is incorrect. Correct encoding is inline constant.

When a FP literal is encountered as a 64-bit src operand, relevant double
number is used by the SP (ALU of AMDGPU), regardless of the operand type. If an
operand is not F64, then 64-bit representation of double number is used.

In practice, such kind of operands are rarely used, so importance is low
(P=enhancement). Number of failing lit1 tests (-search=simple) = 2513.

I am almost sure that issue appears for other sub-targets as well, e.g. gfx8. 

Lit1 tests attached.

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