[llvm-bugs] [Bug 28098] Inline assembly, instruction order and register clobbering on Aarch64

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=28098

Eric Christopher <echristo at gmail.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
                 CC|                            |echristo at gmail.com
         Resolution|---                         |INVALID

--- Comment #2 from Eric Christopher <echristo at gmail.com> ---
Hi Pavel,

As background, in general, inline asm is an opaque box to the optimizer and
code generator. This means that while "any blr instruction" could clobber x8,
the compiler doesn't parse and optimize your inline assembly to figure out what
you've done and the implications.

So I believe this is "works as intended" here. What's going on is that the call
to puts is clobbering the value in x8 and there's no clobber in the inline asm
statement so the compiler doesn't know that it's being clobbered there. The
inline asm is also not marked as volatile so the compiler feels free to move
things that aren't directly affected above the inline asm statement.

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