[llvm-bugs] [Bug 28557] New: FixupSetCC miscompile

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=28557

            Bug ID: 28557
           Summary: FixupSetCC miscompile
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: jvanadrighem at gmail.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Created attachment 16746
  --> https://llvm.org/bugs/attachment.cgi?id=16746&action=edit
Minimal Repro

For the reproducer here it looks like the xorl is being placed above the place
we set register value:
        xorl    %edx, %edx
        movq    (%rax), %rax
        movq    %rdi, %rdx
        orq     96(%rbp), %rdx
        movq    %rax, -48(%rbp)
        setne   %sil
        xorl    %ebx, %ebx
        movslq  (%r8), %rcx
        movb    %sil, -113(%rbp)
        movb    %sil, %dl
Built with O2, but seems to happen with O3 as well. I tried to reduce the case
as much as possible but this is as minimal as I could get with abtest.py +
creduce + manual edits.

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