[llvm-bugs] [Bug 26091] New: X86 scheduler causes mass spill/fills in test/CodeGen/X86/vector-sext.ll after r255761
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llvm-bugs at lists.llvm.org
Fri Jan 8 15:15:28 PST 2016
https://llvm.org/bugs/show_bug.cgi?id=26091
Bug ID: 26091
Summary: X86 scheduler causes mass spill/fills in
test/CodeGen/X86/vector-sext.ll after r255761
Product: new-bugs
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: new bugs
Assignee: unassignedbugs at nondot.org
Reporter: evstupac at gmail.com
CC: llvm-bugs at lists.llvm.org
Classification: Unclassified
2 functions affected compiled with "-mtriple=x86_64-unknown-unknown
-mattr=+avx2":
"load_sext_16i1_to_16i16" and "load_sext_32i1_to_32i8"
For example in "load_sext_16i1_to_16i16" before the patch applied compiler do
sign extensions one-by-one and therefore do not need much registers:
movzwl (%rdi), %eax <-----
movq %rax, %rcx
shlq $54, %rcx
sarq $63, %rcx
movq %rax, %rdx <-----
shlq $55, %rdx
sarq $63, %rdx
vmovd %edx, %xmm0
vpinsrw $1, %ecx, %xmm0, %xmm0
movq %rax, %rcx <-----
shlq $53, %rcx
sarq $63, %rcx
vpinsrw $2, %ecx, %xmm0, %xmm0
...........
After the patch was applied:
All initializations with %rax are moved to the beginning extending registers
life and therefore overall register pressure:
movswq (%rdi), %rax
movq %rax, %rcx
shlq $55, %rcx
sarq $63, %rcx
vmovd %ecx, %xmm0
movq %rax, %r8
movq %rax, %r10
movq %rax, %r11
movq %rax, %r14
movq %rax, %r15
movq %rax, %r9
movq %rax, %r12
movq %rax, %r13
movq %rax, %rbx
movq %rax, %rdi
movq %rax, %rcx
movq %rax, %rdx
movq %rax, %rsi
movsbq %al, %rbp
shlq $54, %rax
sarq $63, %rax
vpinsrw $1, %eax, %xmm0, %xmm0
shlq $53, %r8
sarq $63, %r8
vpinsrw $2, %r8d, %xmm0, %xmm0
The applied patch is not related to scheduler and only uncover the issue.
There is no this issue if we pass "-enable-misched=0" option.
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