[llvm-bugs] [Bug 26500] New: PowerPC64: CR spill code causes SEGV

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=26500

            Bug ID: 26500
           Summary: PowerPC64: CR spill code causes SEGV
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PowerPC
          Assignee: unassignedbugs at nondot.org
          Reporter: anton at samba.org
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

I've seen a few SEGVs when running csmith. In all the cases I have looked at,
we've dereferenced what looks like a condition register value:

One example:

r3             0x42000042

=> 0x0000000010000bdc <+1516>:    lhz     r3,30996(r3)

What is interesting is that the CR spill gets scheduled quite a way into the
function, after we've used r12 for something else. Later on we reuse r12 (which
has now been contaminated with a CR).


Use r12:
    10000734:   ff ff 82 3d     addis   r12,r2,-1

Spill CR using r12 as scratch:
    100007fc:   26 00 80 7d     mfcr    r12
    1000080c:   08 00 81 91     stw     r12,8(r1)

Use value in r12 later on:
    10000914:   a8 00 9f f9     std     r12,168(r31)
    10000bcc:   a8 00 7f e8     ld      r3,168(r31)


LLVM seems to use r12 unconditionally for CR spill, are we missing some sort of
r12 clobber?

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