[llvm-bugs] [Bug 28809] New: [ARM] Partially undef i64 generates invalid str (with source = base).

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=28809

            Bug ID: 28809
           Summary: [ARM] Partially undef i64 generates invalid str (with
                    source = base).
           Product: new-bugs
           Version: 3.8
          Hardware: Other
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: edy.burt at gmail.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

The following function:

char *foo(char *p, char *end, int x) {
  long long h;
  while(p != end) {
    h &= 0xffffffffull;
    *(long long*)(p += x) = h;
  }
  return p;
}

Generates the following assembly on arm-unknown-linux-gnueabihf:

foo(char*, char*, int):                            @ @foo(char*, char*, int)
        cmp     r0, r1
        bxeq    lr
        mov     r3, #0
.LBB0_1:                                @ %.lr.ph
        str     r0, [r0, r2]!
        cmp     r1, r0
        str     r3, [r0, #4]
        bne     .LBB0_1
        bx      lr

The first store, "str     r0, [r0, r2]!", is an invalid opcode.
Trying to put that instruction in inline assembly results in:
> error: source register and base register can't be identical

However, LLVM (3.8 and later, at least) will happily generate the invalid
instruction, which causes SIGILL if it's ever attempted to be executed.

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