[llvm-bugs] [Bug 27484] New: [ARM] Codegen/Thumb/segmented-stacks.ll hits assert when llvm compiled w/ XDEBUG

Fri Apr 22 12:07:14 PDT 2016

https://llvm.org/bugs/show_bug.cgi?id=27484

            Bug ID: 27484
           Summary: [ARM] Codegen/Thumb/segmented-stacks.ll hits assert
                    when llvm compiled w/ XDEBUG
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: gberry at codeaurora.org
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Error message below:

# Machine code for function test_large: Properties: <Post SSA, tracking
liveness, AllVRegsAllocated>
Frame Objects:
  fi#0: size=40000, align=4, at location [SP-40016]
  fi#1: size=4, align=4, at location [SP-4]
  fi#2: size=4, align=4, at location [SP-8]
  fi#3: size=4, align=4, at location [SP-12]
  fi#4: size=4, align=4, at location [SP-16]
Constant Pool:
  cp#0: -40000, align=4
  cp#1: 40000, align=4
  cp#2: __STACK_LIMIT, align=4

BB#1: 
    Live Ins: %R4 %R5 %R6 %LR
    tPUSH pred:14, pred:%noreg, %R4, %R5, %SP<imp-def>, %SP<imp-use>
    CFI_INSTRUCTION <call frame instruction>
    CFI_INSTRUCTION <call frame instruction>
    CFI_INSTRUCTION <call frame instruction>
    Successors according to CFG: BB#2(?%)

BB#2: 
    Live Ins: %R4 %R5 %R6 %LR
    Predecessors according to CFG: BB#1
    %R5<def> = tMOVr %SP, pred:14, pred:%noreg
    %R5<def,tied2> = tSUBi8 opt:%noreg, %R5<tied0>, 40192, pred:14, pred:%noreg
    Successors according to CFG: BB#3(?%)

BB#3: 
    Live Ins: %R4 %R5 %R6 %LR
    Predecessors according to CFG: BB#2
    %R4<def> = tLDRpci <cp#2>, pred:14, pred:%noreg
    %R4<def> = tLDRi %R4, 0, pred:14, pred:%noreg
    tCMPr %R4, %R5, pred:14, pred:%noreg, %CPSR<imp-def>
    tBcc <BB#5>, pred:3, pred:%CPSR
    Successors according to CFG: BB#5(?%) BB#4(?%)

BB#4: 
    Live Ins: %R4 %R5 %R6 %LR
    Predecessors according to CFG: BB#3
    %R4<def> = tMOVi8 opt:%noreg, 40192, pred:14, pred:%noreg
    %R5<def> = tMOVi8 opt:%noreg, 0, pred:14, pred:%noreg
    tPUSH pred:14, pred:%noreg, %LR, %SP<imp-def>, %SP<imp-use>
    CFI_INSTRUCTION <call frame instruction>
    CFI_INSTRUCTION <call frame instruction>
    tBL pred:14, pred:%noreg, <es:__morestack>, %LR<imp-def>, %SP<imp-use>
    tPOP pred:14, pred:%noreg, %R4, %SP<imp-def>, %SP<imp-use>
    %LR<def> = tMOVr %R4, pred:14, pred:%noreg
    tPOP pred:14, pred:%noreg, %R4, %R5, %SP<imp-def>, %SP<imp-use>
    CFI_INSTRUCTION <call frame instruction>
    tBX_RET pred:14, pred:%noreg
    Successors according to CFG: BB#5(?%)

BB#5: 
    Live Ins: %R4 %R5 %R6 %LR
    Predecessors according to CFG: BB#4 BB#3
    tPOP pred:14, pred:%noreg, %R4, %R5, %SP<imp-def>, %SP<imp-use>
    CFI_INSTRUCTION <call frame instruction>
    CFI_INSTRUCTION <call frame instruction>
    CFI_INSTRUCTION <call frame instruction>
    Successors according to CFG: BB#0(?%)

BB#0: derived from LLVM BB %0
    Live Ins: %R4 %R5 %R6 %LR
    Predecessors according to CFG: BB#5
    tPUSH pred:14, pred:%noreg, %R4<kill>, %R5<kill>, %R6<kill>, %LR<kill>,
%SP<imp-def>, %SP<imp-use>; flags: FrameSetup
    CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
    CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
    CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
    CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
    CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
    %vreg0<def> = tLDRpci <cp#0>, pred:14, pred:%noreg; flags: FrameSetup
tGPR:%vreg0
    %SP<def,tied1> = tADDhirr %SP<tied0>, %vreg0<kill>, pred:14, pred:%noreg;
tGPR:%vreg0
    CFI_INSTRUCTION <call frame instruction>; flags: FrameSetup
    %R0<def> = tADDframe <fi#0>, 0, %CPSR<imp-def,dead>
    %R1<def>, %CPSR<def,dead> = tMOVi8 0, pred:14, pred:%noreg
    tBL pred:14, pred:%noreg, <ga:@dummy_use>, <regmask %LR %D8 %D9 %D10 %D11
%D12 %D13 %D14 %D15 %Q4 %Q5 %Q6 %Q7 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R11 %S16 %S17
%S18 %S19 %S20 %S21 %S22 %S23 %S24 %S25 %S26 %S27 %S28 %S29 %S30 %S31 %D8_D10
%D9_D11 %D10_D12 %D11_D13 %D12_D14 %D13_D15 %Q4_Q5 %Q5_Q6 %Q6_Q7 %Q4_Q5_Q6_Q7
%R4_R5 %R6_R7 %R8_R9 %R10_R11 %D8_D9_D10 %D9_D10_D11 %D10_D11_D12 %D11_D12_D13
%D12_D13_D14 %D13_D14_D15 %D8_D10_D12 %D9_D11_D13 %D10_D12_D14 %D11_D13_D15
%D8_D10_D12_D14 %D9_D11_D13_D15 %D9_D10 %D11_D12 %D13_D14 %D9_D10_D11_D12
%D11_D12_D13_D14>, %LR<imp-def,dead>, %SP<imp-use>, %R0<imp-use>, %R1<imp-use>,
%SP<imp-def>
    %vreg1<def> = tLDRpci <cp#1>, pred:14, pred:%noreg; tGPR:%vreg1
    %SP<def,tied1> = tADDhirr %SP<tied0>, %vreg1<kill>, pred:14, pred:%noreg;
tGPR:%vreg1
    tPOP pred:14, pred:%noreg, %R4<def>, %R5<def>, %R6<def>, %SP<imp-def>,
%SP<imp-use>
    tPOP pred:14, pred:%noreg, %R0<def>, %SP<imp-def>, %SP<imp-use>
    %LR<def> = tMOVr %R0<kill>, pred:14, pred:%noreg
    tBX_RET pred:14, pred:%noreg

# End machine code for function test_large.

*** Bad machine code: Function has AllVRegsAllocated property but there are
VReg operands ***
- function:    test_large
LLVM ERROR: Found 1 machine code errors.

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