[llvm-bugs] [Bug 27421] Mips64: Missing sign extension when operand for truncate instruction is in another basic block.

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=27421

Vasileios Kalintiris <Vasileios.Kalintiris at imgtec.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #1 from Vasileios Kalintiris <Vasileios.Kalintiris at imgtec.com> ---
This was fixed in r266203.

I created this PR in order to provide a public point of reference for this bug.

As I explained in my commit, the culprit behind this was the lack of sign
extension on the truncation of i64 values that have been AssertZext'd from an
i32 VT. This is required by the MIPS architecture because instructions
operating
on 32-bit values should have their inputs sign-extended to GPR-width, otherwise
they produce undefined results. See the aforementioned commit, r266203, for
more information.

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