[llvm-bugs] [Bug 24669] New: Invalid optimization on ARM + Neon

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=24669

            Bug ID: 24669
           Summary: Invalid optimization on ARM + Neon
           Product: libraries
           Version: 3.6
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: pitrou at free.fr
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

This is with 3.6.2.  If you take the following IR:

define i32 @get_set_complex({ float, float }* noalias nocapture %retptr,
                            { i8*, i32 }** noalias nocapture readnone %excinfo,
                            i8* noalias nocapture readnone %env,
                            [38 x i8]* nocapture %arg.rec,
                            float %arg.val.0, float %arg.val.1)
{
entry:
  %inserted.real = insertvalue { float, float } undef, float %arg.val.0, 0
  %inserted.imag = insertvalue { float, float } %inserted.real, float
%arg.val.1, 1
  %.15 = getelementptr inbounds [38 x i8]* %arg.rec, i32 0, i32 10
  %.16 = bitcast i8* %.15 to { float, float }*
  %.17 = bitcast i8* %.15 to float*
  %.18 = load float* %.17, align 1
  %.19 = getelementptr inbounds [38 x i8]* %arg.rec, i32 0, i32 14
  %0 = bitcast i8* %.19 to float*
  %.20 = load float* %0, align 1
  %inserted.real.1 = insertvalue { float, float } undef, float %.18, 0
  %inserted.imag.1 = insertvalue { float, float } %inserted.real.1, float %.20,
1
  store { float, float } %inserted.imag, { float, float }* %.16, align 1
  store { float, float } %inserted.imag.1, { float, float }* %retptr, align 4
  ret i32 0
}


and feed it into llc as follows:

$ llc -O3 -code-model=default -relocation-model=default
-mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic


the assembler output is buggy, as it does the loads after the stores:

@ BB#0:                                 @ %entry
    vmov    r1, s1
    str    r1, [r3, #14]
    vmov    r1, s0
    str    r1, [r3, #10]
    ldr    r1, [r3, #10]
    ldr    r2, [r3, #14]
    stm    r0, {r1, r2}
    mov    r0, #0
    bx    lr

If you replace "-O3" with "-O0", you get correct assembler output (loads are
issued before stores):

@ BB#0:                                 @ %entry
    .save    {r11, lr}
    push    {r11, lr}
    movw    r1, #0
    ldr    r2, [r3, #10]
    ldr    r12, [r3, #14]
    vmov    lr, s1
    str    lr, [r3, #14]
    vmov    lr, s0
    str    lr, [r3, #10]
    str    r12, [r0, #4]
    str    r2, [r0]
    mov    r0, r1
    pop    {r11, pc}

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