[LLVMbugs] [Bug 23000] New: Immediates that need shifts are misassembled for ARM

[bugzilla-daemon at llvm.org]

https://llvm.org/bugs/show_bug.cgi?id=23000

            Bug ID: 23000
           Summary: Immediates that need shifts are misassembled for ARM
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: joerg at NetBSD.org
                CC: compnerd at compnerd.org, dimitry at andric.com,
                    llvmbugs at cs.uiuc.edu, t.p.northover at gmail.com
    Classification: Unclassified

Try to assemble:

AES_Te:
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
AES_encrypt:
 sub r10,r3,#(AES_encrypt-AES_Te) @ Te

and disassemble. The immediate for the sub is misencoded. This is observed in
the OpenSSL assembly.

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