[llvm-bugs] [Bug 24465] New: Investigate whether AArch64LoadStoreOptimizer can combine STUR+STR to STP (like STR+STR)

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=24465

            Bug ID: 24465
           Summary: Investigate whether AArch64LoadStoreOptimizer can
                    combine STUR+STR to STP (like STR+STR)
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: ahmed.bougacha at gmail.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

This doesn't generate STP, but it seems like it should:


target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

define float* @foo(float* nocapture %PTR, <4 x float> %VAL1, <4 x float> %VAL2)
{
entry:
  %add.ptr = getelementptr inbounds float, float* %PTR, i64 -4
  %tmp = bitcast float* %add.ptr to <4 x float>*
  store <4 x float> %VAL1, <4 x float>* %tmp, align 16
  %tmp1 = bitcast float* %PTR to <4 x float>*
  store <4 x float> %VAL2, <4 x float>* %tmp1, align 16
  %add.ptr2 = getelementptr inbounds float, float* %PTR, i64 8
  ret float* %add.ptr2
}

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