[llvm-bugs] [Bug 24363] New: [powerpc] missed CSE opportunity in DAG?

[bugzilla-daemon at llvm.org]

https://llvm.org/bugs/show_bug.cgi?id=24363

            Bug ID: 24363
           Summary: [powerpc] missed CSE opportunity in DAG?
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PowerPC
          Assignee: unassignedbugs at nondot.org
          Reporter: spatel+llvm at rotateright.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

While investigating fast-math-flags propagation in the DAG (see r244053), I
noticed that PPC ends up with different code than AArch64 or x86 for this
example:

  define float @fmf(float %a, float %b) {
    %mul1 = fmul fast float %a, %b
    %nega = fsub fast float 0.0, %a
    %mul2 = fmul fast float %nega, %b
    %abx2 = fsub fast float %mul1, %mul2
    ret float %abx2
  }

$ ./llc -o - badflags.ll -march=ppc64 -enable-unsafe-fp-math
...
    fmuls f0, f1, f2
    fmadds f1, f1, f2, f0
    blr

--------------------------------------------------------------------------------

I was expecting to see an 'fadds f1, f0, f0' instead of the 'fmadds' (less
register usage; potentially faster to execute an 'add' than an 'fma').

AArch64 does this:
$ ./llc -o - badflags.ll -march=aarch64 -enable-unsafe-fp-math
...
    fmul    s0, s0, s1
    fadd    s0, s0, s0
    ret

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