[LLVMbugs] [Bug 21277] New: AArch64: "Cannot Select" error for FP conversions from/to vectors of half/f16 operands

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=21277

            Bug ID: 21277
           Summary: AArch64: "Cannot Select" error for FP conversions
                    from/to vectors of half/f16 operands
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: ahmed.bougacha at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

FP conversions involving half/f16 vectors cause the compiler to fail.
My understanding is that these operations aren't legal on AArch64, and should
be legalized before being selected.

This also happens for other targets; half/f16 types don't seem to be properly
legalized.


On inputs similar to:

define <2 x half> @test_sitofp(<2 x i1> %in) {
entry:
  %0 = sitofp <2 x i1> %in to <2 x half>
  ret <2 x half> %0
}

we get:

> LLVM ERROR: Cannot select: 0x7f8a7a814d68: v4f16 = sint_to_fp 0x7f8a7a816410
> [ORD=2] [ID=17]
>   0x7f8a7a816410: v4i32 = insert_vector_elt 0x7f8a7a816308, 0x7f8a7a816728,
> 0x7f8a7a814738 [ORD=2] [ID=16]
>     0x7f8a7a816308: v4i32 = INSERT_SUBREG 0x7f8a7a814630, 0x7f8a7a816a40,
> 0x7f8a7a814948 [ORD=2] [ID=15]
>       0x7f8a7a814630: v4i32 = undef [ID=6]
>       0x7f8a7a816a40: i32 = sign_extend_inreg 0x7f8a7a816830, 0x7f8a7a816620
> [ORD=2] [ID=13]
>         0x7f8a7a816830: i32 = extract_vector_elt 0x7f8a7a814e70, 0x7f8a7a814420
> [ORD=2] [ID=11]
>           0x7f8a7a814e70: v4i32 = insert_subvector 0x7f8a7a814630,
> 0x7f8a7a814108, 0x7f8a7a814318 [ORD=1] [ID=10]
>             0x7f8a7a814630: v4i32 = undef [ID=6]
>             0x7f8a7a814108: v2i32,ch = CopyFromReg 0x7f8a79c16100,
> 0x7f8a7a814000 [ORD=1] [ID=9]
>               0x7f8a7a814000: v2i32 = Register %vreg0 [ID=1]
>             0x7f8a7a814318: i32 = Constant<0> [ID=8]
>           0x7f8a7a814420: i64 = Constant<0> [ID=3]
>       0x7f8a7a814948: i32 = TargetConstant<14> [ID=7]
>     0x7f8a7a816728: i32 = sign_extend_inreg 0x7f8a7a816200, 0x7f8a7a816620
> [ORD=2] [ID=14]
>       0x7f8a7a816200: i32 = extract_vector_elt 0x7f8a7a814e70, 0x7f8a7a814738
> [ORD=2] [ID=12]
>         0x7f8a7a814e70: v4i32 = insert_subvector 0x7f8a7a814630, 0x7f8a7a814108,
> 0x7f8a7a814318 [ORD=1] [ID=10]
>           0x7f8a7a814630: v4i32 = undef [ID=6]
>           0x7f8a7a814108: v2i32,ch = CopyFromReg 0x7f8a79c16100, 0x7f8a7a814000
> [ORD=1] [ID=9]
>             0x7f8a7a814000: v2i32 = Register %vreg0 [ID=1]
>           0x7f8a7a814318: i32 = Constant<0> [ID=8]
>         0x7f8a7a814738: i64 = Constant<1> [ID=4]
>     0x7f8a7a814738: i64 = Constant<1> [ID=4]
> In function: test_sitofp

and on:

define <1 x i64> @test_fptosi(<1 x half> %in) {
entry:
  %0 = fptosi <1 x half> %in to <1 x i64>
  ret <1 x i64> %0
}

we get (after fixing PR20778):

> LLVM ERROR: Cannot select: 0x7f94a903d738: i64 = fp_to_sint 0x7f94a903d108
> [ORD=2] [ID=4]
>   0x7f94a903d108: f16,ch = CopyFromReg 0x7f94a8c15c50, 0x7f94a903d000 
> [ORD=1] [ID=3]
>     0x7f94a903d000: f16 = Register %vreg0 [ID=1]
> In function: test_fptosi

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