[LLVMbugs] [Bug 19761] New: [ARM64] Cortex-a53 schedule mode can't handle NEON post-increment load

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=19761

            Bug ID: 19761
           Summary: [ARM64] Cortex-a53 schedule mode can't handle NEON
                    post-increment load
           Product: new-bugs
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: Hao.Liu at arm.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

For the following test case:
-------------------------------------------------------------------------------
define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
;CHECK-LABEL: test_v16i8_post_imm_ld2:
;CHECK: ld2.16b { v0, v1 }, [x0], #32
  %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8*
%A)
  %tmp = getelementptr i8* %A, i32 32
  store i8* %tmp, i8** %ptr
  ret { <16 x i8>, <16 x i8> } %ld2
}

declare { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8*)
-------------------------------------------------------------------------------

Run with -mcpu=cortex-a53 will result as following:
$ llc -march=arm64 -mcpu=cortex-a53 < ld2.ll
    .text
    .file    "<stdin>"
LLVM ERROR: DefIdx 1 exceeds machine model writes for %vreg2<def,tied2>,
%vreg3<def> = LD2Twov16b_POST %vreg2<tied0>, %XZR; GPR64common:%vreg2 QQ:%vreg3


It seems that there is something wrong within ARM64SchedA53.td.

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