[LLVMbugs] [Bug 19972] New: Bad code generation in post-ra ARMLoadStoreOptimizer pass in thumb1 mode
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Fri Jun 6 13:58:45 PDT 2014
http://llvm.org/bugs/show_bug.cgi?id=19972
Bug ID: 19972
Summary: Bad code generation in post-ra ARMLoadStoreOptimizer
pass in thumb1 mode
Product: new-bugs
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: normal
Priority: P
Component: new bugs
Assignee: unassignedbugs at nondot.org
Reporter: sgundapa at codeaurora.org
CC: llvmbugs at cs.uiuc.edu
Classification: Unclassified
Created attachment 12624
--> http://llvm.org/bugs/attachment.cgi?id=12624&action=edit
Test case to demonstrate the bad codegen
Hi,
Please find the attached test case which can demonstrate the bad code
generation in post-ra ARMLoadStoreOptimizer pass in thumb1 mode.
If I compile with tip, I get this assembly:
$ clang -target arm -Os -mthumb -mcpu=arm926ej-s -c t.c -S -o-
@ BB#0: @ %entry
push {r7, lr}
add r7, sp, #0
subs r0, #8
ldm r0!, {r1, r2}
bl bar
pop {r7, pc}
The base address is incorrectly decremented before the load, so we end up
loading the incorrect values.
If I disable the post-ra ARMLoadStoreOptimizer pass, I get this assembly:
@ BB#0: @ %entry
push {r7, lr}
add r7, sp, #0
ldr r1, [r0]
ldr r2, [r0, #4]
bl bar
pop {r7, pc}
which correctly loads the values.
I would expect the ARMLoadStoreOptimizer to generate assembly like this for the
source code:
push {r7, lr}
add r7, sp, #0
ldm r0, {r1, r2}
bl bar
pop {r7, pc}
I triage the commit which initially caused the bad codegen.
The commit is
commit 40ae57cc0a187424c8db723a51506b7192b77f71
Author: James Molloy <james.molloy at arm.com>
Date: Fri May 16 14:14:30 2014 +0000
Fix the Load/Store optimization pass to work with Thumb1.
Patch by Moritz Roth!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208992
91177308-0d34-0410-b5e6-96231b3b80d8
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