[LLVMbugs] [Bug 20308] New: Bug in PostRA scheduler on spec2000 255.vortex

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http://llvm.org/bugs/show_bug.cgi?id=20308

            Bug ID: 20308
           Summary: Bug in PostRA scheduler on spec2000 255.vortex
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: avolkov.intel at gmail.com
                CC: hfinkel at anl.gov, llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Created attachment 12766
  --> http://llvm.org/bugs/attachment.cgi?id=12766&action=edit
test

There was a regression on 255.vortex when compiling for x86 Silvermont
processor.
It was happenned after the following commit of Hal Finkel:
Author: Hal Finkel <hfinkel at anl.gov>
Date:   Mon Mar 31 23:23:51 2014 +0000

    Move partial/runtime unrolling late in the pipeline

    The generic (concatenation) loop unroller is currently placed early in the
    standard optimization pipeline. This is a good place to perform full
unrolling,
    but not the right place to perform partial/runtime unrolling. However, most
    targets don't enable partial/runtime unrolling, so this never mattered.

    However, even some x86 cores benefit from partial/runtime unrolling of very
    small loops, and follow-up commits will enable this. First, we need to move
    partial/runtime unrolling late in the optimization pipeline (importantly,
this
    is after SLP and loop vectorization, as vectorization can drastically
change
    the size of a loop), while keeping the full unrolling where it is now. This
    change does just that.

    git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205264
91177308-0d34-0410-b5e6-96231b3b80d8

The root cause of failure is wrong code after PostRA schedule:
Before PostRA:
        %RAX<def> = MOV64rm %RIP, 1, %noreg, <ga:@Part_Class>[TF=5], %noreg;
mem:LD8[GOT]
        %RDI<def> = KILL %RBP
        CALL64pcrel32 <ga:@Object_NewImage>[TF=6], <regmask>, %RSP<imp-use>,
%RDI<imp-use>, %ESI<imp-use>, %EDX<imp-use>, %ECX<imp-use>, %R8<imp-use,kill>,
%R9<imp-use,kill>, %RSP<imp-def>, %EAX<imp-def>
After PostRA:
        %RDI<def> = MOV64rm %RIP, 1, %noreg, <ga:@Part_Class>[TF=5], %noreg;
mem:LD8[GOT]
        %RDI<def> = KILL %RBP
        CALL64pcrel32 <ga:@Object_NewImage>[TF=6], <regmask>, %RSP<imp-use>,
%RDI<imp-use,kill>, %ESI<imp-use,kill>, %EDX<imp-use,kill>, %ECX<imp-use,kill>,
%R8<imp-use,kill>, %R9<imp-use,kill>, %RSP<imp-def>, %EAX<imp-def>

For some reason PostRA scheduler changes register for MOV64rm from RAX to RDI.
It causes wrong value passed to Object_NewImage call later since KILL
instruction lowered to nothing in assembler.

I attached test.ll file and file with IR, use the following command to
reproduce:
llc -O2 -mcpu=slm -relocation-model=pic test.ll

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